Multilayer Ceramic Capacitor Electrode Asymmetry
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Solution Overview
Problem
Existing multilayer ceramic capacitors have insufficient withstand voltage due to stress caused by electrostrictive effects, leading to reduced performance and reliability.
Innovation Solution
A multilayer ceramic capacitor design with alternately stacked dielectric and internal electrode layers, where the edges of internal electrodes are positioned to maximize the distance between outermost and innermost edges in both the Y and X directions, and the curvature radius of corners is larger than the edge deviations, dispersing stress and enhancing withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If internal electrodes are arranged with coinciding sides in a stack direction, then manufacturing is simplified, but stress concentration occurs at electrode edges reducing withstand voltage
Solution Approach 1:
The patent applies asymmetry by intentionally designing internal electrodes with non-coinciding sides in the stack direction. Specifically, the electrodes are arranged such that their edges are offset from each other, creating an asymmetric pattern that prevents stress concentration at any single edge location. This asymmetric arrangement directly addresses the withstand voltage issue while accepting increased manufacturing complexity as a trade-off.
Solution Approach 2:
The patent applies curvature by rounding the corner portions of internal electrodes with a specified radius of curvature. This spherical/curved design replaces sharp corners that would concentrate stress, thereby improving withstand voltage. The rounded edges distribute electrical stress more evenly throughout the dielectric material, preventing breakdown at critical stress points.
2Quantity of substance
If overlap area of internal electrodes is enlarged, then capacitance increases, but stress concentration at edges increases reducing withstand voltage
Solution Approach 1:
The patent resolves this contradiction by using asymmetric electrode arrangement where edges are offset in the stack direction. This allows the overlap area to be enlarged for higher capacitance while the asymmetric positioning prevents stress concentration at any single edge, thereby maintaining high withstand voltage despite the increased overlap area.
Solution Approach 2:
The patent uses rounded corner portions with specified curvature radius to mitigate edge stress concentration. This allows the electrodes to have larger overlap areas for increased capacitance while the curved edges prevent stress concentration that would otherwise occur at sharp corners, thus maintaining high withstand voltage.
3Ease of manufacture
If sides of internal electrodes coincide in stack direction, then manufacturing alignment is easier, but electrostrictive stress concentrates at edges
Solution Approach 1:
The patent deliberately introduces asymmetry by offsetting the sides of internal electrodes in the stack direction. This asymmetric design prioritizes electrical performance (withstand voltage) over manufacturing simplicity, accepting that alignment may be slightly more complex while achieving significantly improved stress distribution and higher breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively disperses stress caused by electrostrictive effects, significantly improving the withstand voltage of the multilayer ceramic capacitor, enabling higher operational voltages and capacities while maintaining structural integrity.
Implementation Method 1
a multilayer ceramic capacitor includes: a multilayer structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked
Implementation Method 2
The design effectively disperses stress caused by electrostrictive effects
Data Source
AI summary
A multilayer ceramic capacitor includes a multilayer structure wherein [t12×L1]/N≥10, when a distance between a first edge that is an outermost edge of internal electrodes that is not connected to a first or second external electrode and a second edge that is an innermost edge of the internal electrodes that is not connected to the first or second external electrode is L1, each thickness of dielectric layers is t1, and a stack number of dielectric layers is N, wherein [t12×W1]/N≥10, when a distance between a first edge that is positioned at outermost of the internal electrodes and a second edge that is positioned at innermost of the internal electrodes is W1, and wherein R is larger than W1, when a curvature radius of a corner of an edge of the internal electrodes is R.