Multilayer Ceramic Capacitor Margin Structure for Shrinkage Control
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Solution Overview
Problem
Multilayer ceramic electronic components face structural deformation and short circuit issues due to differences in firing shrinkage between ceramic and metal components, affecting capacitance and electrical characteristics, especially as component sizes decrease.
Innovation Solution
A multilayer ceramic electronic component design that satisfies the formula −0.1≤(Tm−Ta)/Ta, where Tm is the average height of the margin portion and Ta is the average height of the capacitance formation portion, to minimize structural deformation and improve withstand voltage by controlling the ratio of margin and capacitance formation heights, thereby reducing compressive stress and grain size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simultaneous sintering is used to manufacture multilayer ceramic electronic components, then manufacturing efficiency is improved, but structural deformation and short circuit defects occur due to different shrinkage rates between ceramic and metal components
Solution Approach 1:
The patent applies parameter changes by controlling the ratio (Tm-Ta)/Ta where Tm is the average height of the margin portion and Ta is the average height of the capacitance formation portion. By optimizing this geometric parameter within a specific range, the patent compensates for the different shrinkage rates of ceramic and metal components during sintering, reducing structural deformation while maintaining manufacturing efficiency.
2Volume of moving object
If component size is reduced to achieve miniaturization, then product size is improved, but reliability and quality deteriorate due to increased sensitivity to shrinkage differences
Solution Approach 1:
The patent uses parameter changes by establishing a specific range for the height ratio (Tm-Ta)/Ta of the margin portion. This parameter control becomes increasingly critical as component size decreases, as the relative impact of shrinkage differences is magnified in smaller components. By maintaining this parameter within the specified range, the patent ensures consistent quality and reliability even as components are miniaturized.
3Strength
If margin portion height is increased to reduce compressive stress, then withstand voltage characteristics are improved, but capacitance formation area is reduced
Solution Approach 1:
The patent applies parameter changes by optimizing the height ratio (Tm-Ta)/Ta within a specific range. This optimization balances two competing requirements: increasing the margin portion height to reduce compressive stress and improve withstand voltage, while maintaining sufficient capacitance formation area. The patent identifies the optimal parameter range that achieves both goals simultaneously, rather than maximizing one at the expense of the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces structural deformation, short circuit rates, and enhances withstand voltage characteristics, improving the reliability and quality of multilayer ceramic electronic components.
Implementation Method 1
The multilayer ceramic electronic component includes a dielectric ceramic, an internal electrode, and an external electrode, and is generally manufactured by simultaneous sintering
Implementation Method 2
the ceramic component and the metal component have different shrinkage initiation temperatures during sintering and a shrinkage rate is often different
Data Source
AI summary
A multilayer ceramic electronic component includes: a ceramic body having a capacitance formation portion, and including a dielectric layer and a first internal electrode and a second internal electrode with the dielectric layer interposed therebetween, a first margin portion disposed on the surface of the capacitance formation portion, and a second margin portion disposed on the other surface of the capacitance formation portion; a first external electrode; and a second external electrode. A following formula 1 is satisfied, [formula 1]−0.1≤(Tm−Ta)/Ta, where in the formula 1, Tm is an average height of a central region of the margin portion, and Ta is an average height of an outer region of the capacitance formation portion in a second direction.