3D Ceramic Power Module Stacking for Thermal Stress Reduction
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Solution Overview
Problem
Current power module encapsulation techniques face challenges in managing thermomechanical stresses due to material expansion coefficients, achieving accurate relative positioning of components, and efficiently cooling high-temperature, high-voltage, and high-frequency applications, while also ensuring mechanical strength and electrical interconnection.
Innovation Solution
A method involving three-dimensional printing or powder injection molding of ceramic supports with metallized reliefs and cooling fins, where brazing pastes are used to fix and electrically connect chips, and an encapsulation material is injected between supports to enhance cooling and reduce footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If traditional encapsulation techniques are used, then manufacturing simplicity is maintained, but thermal management capability deteriorates
Solution Approach 1:
The patent transitions from traditional two-dimensional planar encapsulation to a three-dimensional stacked architecture. Multiple ceramic substrates are arranged vertically with chips positioned between them, enabling heat dissipation from both top and bottom surfaces simultaneously. This dimensional change allows independent cooling paths for different chips, significantly improving thermal management capability while the modular nature keeps manufacturing manageable.
2Temperature
If three-dimensional stacked architecture is implemented, then cooling efficiency is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The patent incorporates positioning protrusions and corresponding positioning recesses on the ceramic substrates before the actual assembly process. These pre-formed mechanical guides ensure that when substrates are stacked, the chips and electrical connections automatically align to the correct positions. This preliminary action eliminates the need for high-precision alignment during assembly, reducing manufacturing precision requirements while maintaining accurate relative positioning.
3Temperature
If multiple ceramic substrates with copper layers are used, then thermal management is enhanced, but thermomechanical stresses increase
Solution Approach 1:
The patent applies different material properties to different regions of the ceramic substrates. Specifically, certain areas are designed with rubber-like material characteristics that provide mechanical compliance and stress absorption. This local quality variation allows the structure to accommodate thermal expansion differences between materials while maintaining overall structural integrity, thereby reducing thermomechanical stresses in the stacked architecture.
4Reliability
If complex copper layer patterns are defined, then electrical interconnection capability is improved, but manufacturing complexity worsens
Solution Approach 1:
The patent pre-defines the copper layer patterns on the ceramic substrates during the substrate manufacturing process itself, rather than adding them later. The copper layers are formed with the required electrical connection patterns already integrated into the substrate structure. This preliminary action simplifies subsequent assembly steps and reduces manufacturing complexity while ensuring reliable electrical interconnections between chips and substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides enhanced thermal management, mechanical strength, and accurate component positioning, enabling reliable operation of high-temperature and high-frequency power modules with reduced thermomechanical stresses and surface footprint.
Implementation Method 1
By brazing, the first bump of each copper layer is fixed to a respective face of the chip, and the second bumps and the third bumps of these facing layers of copper are mutually fixed.
Implementation Method 2
an insulating substrate allowing both the electrical insulation and the transfer of the heat flux given off by the chips
Implementation Method 3
a sole plate for a link to a heat sink
Data Source
AI summary
A method for encapsulating an integrated circuit includes: forming first and second electrically insulating supports each having a planar surface, so as to form a recess in the first support with respect to its planar surface, and so as to form, with respect to the planar surface of each of the first and second supports, first and second reliefs, so that the first and second reliefs of the supports interact; forming a first electrical contact in the recess; positioning a chip in the recess; forming a second electrical contact on the second carrier; and superposing the first and second carriers so as to superpose their reliefs.