Ceramic Substrate Stack for Faster Etching and Direct Chip Cooling
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Solution Overview
Problem
Existing ceramic substrates with thick upper metal layers for high-thermal conductivity require lengthy etching processes, leading to inefficiency and increased costs, and they do not effectively manage high-temperature heat generated by semiconductor chips in power modules.
Innovation Solution
A ceramic substrate unit with a bonded wiring unit comprising an insulating layer and electrode layer, connected to a semiconductor chip without etching, and a heat sink for efficient heat dissipation using liquid coolant, allowing for direct cooling and stable bonding at high temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a thick upper metal layer is used for high thermal conductivity, then heat dissipation performance is improved, but etching time increases significantly
Solution Approach 1:
The patent divides the original single thick metal layer into multiple thinner metal layers (first upper metal layer and second upper metal layer) separated by an insulating layer. This segmentation allows each layer to be etched independently in shorter time, while the stacked structure maintains the overall thermal conductivity needed for heat dissipation.
Solution Approach 2:
The patent transitions from a single-plane thick metal structure to a multi-layer stacked structure in the vertical dimension. By distributing the thermal conduction function across multiple layers separated by insulating layers, the design achieves both reduced etching time and maintained heat dissipation performance through the cumulative effect of multiple conductive paths.
2Temperature
If a thick upper metal layer is used for high thermal conductivity, then heat dissipation performance is improved, but manufacturing efficiency deteriorates
Solution Approach 1:
The patent segments the thick metal layer into multiple thinner layers with insulating layers in between. Each layer can be manufactured and etched independently using standard thin-film processes, avoiding the need for lengthy etching of a single thick layer, thus improving manufacturing efficiency while maintaining thermal performance.
Solution Approach 2:
The insulating layers are formed between the metal layers during the manufacturing process, allowing subsequent etching steps to work on thinner layers that require less time. This preliminary structuring of multiple thin layers prepares the structure for more efficient downstream processing.
3Reliability
If a separate wiring unit is bonded to the upper metal layer for circuit connection, then electrical connection is achieved, but device complexity and cost increase
Solution Approach 1:
The patent merges the upper metal layers with the wiring structure by forming electrode layers directly on the insulating layers within the stacked metal structure. This integration eliminates the need for separate wiring units to be bonded onto the upper metal layer, reducing structural complexity and potential bonding failure points while maintaining reliable electrical connections.
Solution Approach 2:
The upper metal layers serve dual functions: providing thermal conduction pathways and forming part of the electrical wiring structure through integrated electrode layers. This multi-functionality eliminates the need for separate dedicated wiring components, simplifying the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces etching time, enhances thermal stability, minimizes inductance, and improves reliability by directly connecting semiconductor chips, while providing efficient heat dissipation and cooling, suitable for high-power applications.
Implementation Method 1
a plurality of protrusions arranged on a bottom surface of the flat portion at intervals, and configured to form a path through which liquid coolant flows
Implementation Method 2
the liquid coolant circulating through the coolant circulation unit may perform heat exchange with the plurality of protrusions
Implementation Method 3
an upper metal layer bonded to a top surface of the ceramic base and configured to allow a semiconductor chip to be mounted thereon
Implementation Method 4
the bonding layer is any one of a brazing filler layer, an Ag sintered layer, and a solder layer
Data Source
AI summary
The present disclosure relates to a ceramic substrate unit and a method of manufacturing the same, and is configured such that the ceramic substrate unit includes a ceramic base, an upper metal layer bonded to a top surface of the ceramic base and configured to allow a semiconductor chip to be mounted thereon, a wiring unit including an insulating layer and an electrode layer arranged on the insulating layer, and bonded to a top surface of the upper metal layer, and a heat sink bonded to a bottom surface of the ceramic base, wherein the electrode layer of the wiring unit is connected to the semiconductor chip to form wiring.