Continuous Execution Set Architecture for Parallel Instruction Scheduling
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Solution Overview
Problem
Conventional Instruction Level Parallelism (ILP) architectures, such as SuperScalar and VLIW, face challenges with complexity and resource inefficiency, particularly in neural network processing units (NPUs) where each instruction operates on 512 variables, requiring up to 2048 cycles, and waste memory and computation resources.
Innovation Solution
The Continuous Execution Set (CES) architecture uses an indication bit within each instruction to dynamically schedule data-independent instructions for parallel execution, eliminating the need for padding bits and reducing hardware resource usage by allowing only one extra bit per instruction for parallelism indication, enabling efficient ILP exploration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SuperScalar architecture dynamically analyzes and schedules instructions for parallel execution, then instruction level parallelism is achieved, but hardware complexity and time cost increase significantly
Solution Approach 1:
The compiler performs preliminary analysis and scheduling of instructions during code generation, identifying data-independent instructions and assigning them to different execution slots before runtime. This eliminates the need for complex runtime dependency checking hardware, as the parallel execution schedule is predetermined by the compiler.
Solution Approach 2:
The patent introduces an intermediary mechanism where the compiler generates special marker instructions that encode parallel execution information. These markers serve as intermediaries between the linear instruction stream and the parallel execution units, allowing simple hardware to achieve complex parallelism behavior without requiring sophisticated dependency analysis logic.
2Productivity
If VLIW architecture packs multiple instructions into parallel execution, then instruction level parallelism is achieved, but memory space and computation resources are wasted
Solution Approach 1:
The patent segments the instruction stream into groups of data-independent instructions that can be executed in parallel, with each segment marked by special indicator bits. This segmentation allows the hardware to execute only the necessary parallel instructions without wasting resources on padding or unused execution slots, unlike traditional VLIW that requires fixed-width instruction words.
Solution Approach 2:
Instead of always packing fixed numbers of instructions into VLIW words, the patent uses partial action by dynamically determining the actual number of parallel instructions needed based on data dependency analysis. The indicator bits specify exactly how many instructions should be executed in parallel, avoiding the resource waste associated with over-provisioning execution slots.
3Ease of operation
If conventional ILP architectures use padding bits to align instructions, then parallel execution is simplified, but instruction encoding efficiency decreases
Solution Approach 1:
The patent applies local quality by inserting indicator bits only at specific locations within the instruction stream where parallel execution groups begin or end, rather than using uniform padding throughout. This localized approach maintains ease of parallel execution control while minimizing the overall encoding space consumed, as indicators are placed only where necessary to delimit parallel instruction groups.
Data Source
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AI summary
The present disclosure provides systems and methods for executing instructions. The system can include: processing unit having a core configured to execute instructions; and a host unit configured to: compile computer code into a plurality of instructions that includes a set of instructions that are determined to be executed in parallel on the core, wherein the set of instructions each includes an operation instruction and an indication bit and wherein the indication bit is set to identify the last instruction of the set of instructions, and provide the set of instructions to the core.