CFET Conductive Line Layout With Asymmetric Front-Back Routing
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Solution Overview
Problem
The existing integrated circuit (IC) designs face challenges in optimizing the performance and flexibility of complementary field-effect transistor (CFET) devices, particularly in reducing resistance and signal interference, while maintaining compact design and routing efficiency.
Innovation Solution
The implementation of asymmetric front-side and back-side conductive line arrangements, including power, signal, and shielding lines, which allow for flexible pitch and reduced redesign costs, along with methods for signal connection between transistors such as source/drain terminal connections, gate connections, and vias, enhances CFET performance and routing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If symmetric front-side and back-side conductive line arrangements are used, then manufacturing simplicity is maintained, but resistance and signal interference increase
Solution Approach 1:
The patent applies asymmetry by configuring the front-side conductive lines (power, signal, shielding) with different patterns and positions than the back-side conductive lines. Specifically, the front-side has a shielding line adjacent to signal lines while the back-side uses a different arrangement, creating asymmetric current paths that reduce signal interference and resistance without requiring complete redesign of the entire conductive system
Solution Approach 2:
The patent implements local quality by optimizing specific regions of the conductive line arrangement rather than applying uniform symmetry throughout. The front-side and back-side have locally differentiated configurations where shielding lines are positioned adjacent to signal lines in specific areas, and power lines are routed through different paths, allowing targeted reduction of resistance and interference in critical regions
2Adaptability or versatility
If compact CFET design is maintained, then area efficiency is improved, but routing flexibility and pitch optimization are limited
Solution Approach 1:
The patent utilizes the vertical dimension by implementing asymmetric conductive line arrangements on both front-side and back-side of the CFET structure. This allows routing flexibility to be achieved through vertical stacking and layered configurations rather than lateral expansion, enabling pitch optimization and routing adaptability while maintaining compact cell footprint and height
3Reliability
If conventional conductive line arrangements are used, then design simplicity is maintained, but resistance and signal interference increase
Solution Approach 1:
The patent applies preliminary action by pre-configuring asymmetric conductive line arrangements with optimized shielding line positions and power line routing paths during the design phase. This preliminary optimization of the conductive topology reduces resistance and signal interference before manufacturing, improving CFET performance without requiring costly post-manufacturing redesign or reconfiguration
Data Source
AI summary
A circuit structure includes a substrate that includes a first transistor stack over the substrate that includes: a first transistor where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type. The structure also includes a plurality of first conductive lines in a first metal layer above the first transistor stack, the plurality of first conductive lines electrically connected to the first transistor stack. The structure also includes a plurality of second conductive lines in a second metal layer below the substrate and underneath the first transistor stack, the plurality of second conductive lines electrically connected to the first transistor stack. The plurality of first conductive lines are configured asymmetrically with respect to the plurality of second conductive lines.