C-FET Channel Width Diversification for SRAM Current Ratio
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Solution Overview
Problem
Existing complementary field effect transistor (C-FET) structures and fabrication processes are inadequate in achieving optimal performance in sub-10 nanometer technology nodes, particularly in static random access memory (SRAM) applications where the on-state current of p-type devices is not adequately smaller than that of n-type devices.
Innovation Solution
The fabrication process involves selectively depositing dielectric layers to modify strain on channel regions, epitaxially growing source/drain features in different environments, and varying channel widths to create transistors with different performance attributes, such as forming bottom and top transistors with distinct channel widths and doping types to achieve optimal on-state current ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing C-FET structures and fabrication processes are used, then manufacturing simplicity is maintained, but the on-state current ratio between p-type and n-type devices is inadequate for optimal SRAM performance
Solution Approach 1:
The patent applies local quality by creating different channel widths for bottom and top transistors within the same C-FET structure. The first channel region has a first channel width while the second channel region has a second channel width different from the first, allowing each transistor to have optimized performance characteristics for its specific function in the SRAM cell
Solution Approach 2:
The patent segments the channel structure into distinct first and second channel regions with different widths. This segmentation allows independent optimization of n-type and p-type transistor characteristics, enabling the p-type device on-state current to be approximately half that of the n-type device for optimal SRAM operation
2Reliability
If channel widths are varied to achieve different performance attributes, then device performance diversification is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by forming a mandrel structure before the channel regions, using it as a template to define the channel widths. The first and second channel regions are formed with different widths based on this preliminary structure, ensuring precise dimensional control while simplifying the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of SRAM cells by ensuring the on-state current of p-type devices is about half that of n-type devices, thereby improving overall device efficiency and performance.
Implementation Method 1
selectively depositing dielectric layers to modify strain on channel regions
Implementation Method 2
epitaxially growing source/drain features in different environments
Data Source
AI summary
Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer and including a channel region sandwiched between a first source/drain region and a second source/drain region, a first plurality of nanostructures disposed over the channel region, a first leakage block layer over the first source/drain region, a second leakage block layer over the second source/drain region, a dielectric layer on the first leakage block layer, a first source/drain feature on the dielectric layer and in contact with first sidewalls of the first plurality of nanostructures, and a second source/drain feature disposed on the second leakage block layer and in contact with second sidewalls of the first plurality of nanostructures. The first leakage block layer and the second leakage block layer includes an undoped semiconductor material.