CFET Gate Stack Oxynitride Barrier Against Dipole Diffusion
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating complementary field-effect transistors (CFETs) due to diffusion issues of dipole layer atoms into the channel layer, which affect device performance and reliability, particularly in high-density integrated circuits.
Innovation Solution
A plasma-formed interfacial oxynitride layer is introduced under the dipole layer to prevent atom diffusion, enhancing mobility and reducing gate leakage and positive bias temperature instability (PBTI) by blocking dipole dopants from entering the channel layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dipole layer is formed to adjust threshold voltage, then device performance is improved, but atom diffusion into the channel layer occurs causing reliability issues
Solution Approach 1:
An oxynitride interfacial layer is introduced between the dipole layer and the channel layer to act as a diffusion barrier. This intermediary layer prevents dipole layer atoms from diffusing into the channel layer while maintaining the threshold voltage adjustment functionality of the dipole layer, thereby resolving the reliability issue caused by atom diffusion.
Solution Approach 2:
The gate dielectric structure is segmented into multiple functional layers: the channel layer, the oxynitride interfacial layer, and the dipole layer. This segmentation allows each layer to perform its specific function independently - the oxynitride layer provides diffusion protection while the dipole layer provides threshold voltage control, eliminating the harmful interaction between them.
2Reliability
If conventional annealing processes are used, then dipole dopants are activated, but thermal budget increases affecting other device components
Solution Approach 1:
Conventional thermal annealing is replaced with plasma-based annealing processes. The plasma provides both heating and reactive species that activate dipole dopants at lower temperatures, reducing the thermal budget impact on other device components while achieving the necessary dopant activation for reliable device operation.
Solution Approach 2:
The annealing process parameters are changed from purely thermal to plasma-enhanced conditions. By introducing reactive plasma species and controlling plasma power and pressure parameters, dopant activation is achieved at lower effective temperatures, thereby reducing the overall thermal budget and preventing damage to temperature-sensitive device structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The oxynitride layer effectively blocks dipole dopants, improving mobility performance and reducing gate leakage and PBTI issues in CFETs, while maintaining a low thermal budget through microwave annealing.
Implementation Method 1
A plasma-formed interfacial oxynitride layer is introduced under the dipole layer to prevent atom diffusion
Implementation Method 2
maintaining a low thermal budget through microwave annealing
Data Source
AI summary
A method includes forming a fin structure including first and second sacrificial layers and first and second channel layers over a substrate; forming a dummy gate structure across the fin structure; forming gate spacers on opposite sides of the dummy gate structure; forming first source/drain epitaxial layers on opposite sides of the first channel layer; forming second source/drain epitaxial layers on opposite sides of the second channel layer; removing the dummy gate structure and the first and second sacrificial layers to form a gate trench defined by the gate spacers; forming an oxynitride layer in the gate trench to surround the first channel layer; forming a dipole layer to surround the oxynitride layer; performing an anneal process to drive dipole dopants into the oxynitride layer; and depositing a high-k gate dielectric layer and a work function metal layer in the gate trench to form a gate structure.