Hybrid Nanostructure CFET Isolation for Stable Threshold Voltage
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Solution Overview
Problem
Forming gate electrodes in complementary field effect transistors (CFETs) with desired characteristics is challenging, leading to improper functioning of stacked transistors, and there is a risk of interference between gate metals affecting the threshold voltage of one transistor by the other.
Innovation Solution
Incorporating an isolation structure between the semiconductor nanostructures of vertically stacked transistors in a CFET, which separates the channel regions and prevents interference between gate metals, ensuring proper functioning and reduced gate-to-drain capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate electrodes are formed in stacked transistors to increase transistor density, then the computing power and integration density are improved, but the gate metals may interfere with each other affecting the threshold voltage and causing improper transistor functioning
Solution Approach 1:
The patent divides the gate electrode structure into two separate segments: a first gate electrode for the first transistor and a second gate electrode for the second transistor. These segmented gates are positioned at different vertical levels, with the second gate extending laterally beyond the first gate. This segmentation prevents the gate metals from interfering with each other while maintaining high transistor density through vertical stacking.
Solution Approach 2:
The patent transitions from a planar gate configuration to a three-dimensional stacked configuration. The second gate electrode is positioned in a different vertical dimension relative to the first gate electrode, allowing both gates to coexist without lateral interference. This dimensional change enables increased transistor density while preserving individual gate control and preventing threshold voltage interference.
2Area of stationary object
If vertical stacking of transistors is implemented to increase density, then the area utilization is improved, but the formation of gate electrodes with desired characteristics becomes difficult
Solution Approach 1:
The gate electrode formation process is segmented into two independent formation steps. The first gate electrode is formed and patterned, then the second gate electrode is formed separately with extended lateral dimensions. This segmentation allows each gate to be independently optimized and formed with precise characteristics, overcoming the difficulties of forming both gates simultaneously in a stacked configuration.
Solution Approach 2:
The first gate electrode is formed in advance before the second gate electrode. This preliminary action allows the first gate to be established with its desired characteristics, and then the second gate is added subsequently with its own optimized formation process. This sequential preliminary action simplifies the overall manufacturing precision requirements compared to simultaneous formation.
Data Source
AI summary
An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor having a first semiconductor nanostructure corresponding to a channel region of the first semiconductor nanostructure and a first gate metal surrounding the second semiconductor nanostructure. The CFET includes a transistor including a second semiconductor nanostructure above the first semiconductor nanostructure and a second gate metal surrounding the second semiconductor nanostructure. The CFET includes an isolation structure between the first and second semiconductor nanostructures.