CFET Mask ROM Cell With Stacked 3D Transistors
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Solution Overview
Problem
The scaling down of transistor gate length in semiconductor storage devices has led to increased off-current and power consumption, necessitating the development of three-dimensional transistors to address these issues.
Innovation Solution
A layout structure for a mask ROM using complementary FET (CFET) devices, where three-dimensional transistors are stacked vertically, with channel portions overlapping each other, and local interconnects connecting sources and drains to bit lines and ground power supply lines, allowing for data storage based on connection states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor gate length is scaled down to improve integration density and operating speed, then integration degree and operating speed are improved, but off current increases and power consumption increases significantly
Solution Approach 1:
The patent transitions from planar two-dimensional transistor structures to three-dimensional vertically stacked CFET structures. By stacking p-type and n-type FETs vertically, the invention achieves higher integration density while maintaining lower off-current through the three-dimensional channel configuration, thus resolving the contradiction between integration density and power consumption.
2Ease of manufacture
If planar transistor structure is used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent employs vertically stacked CFET structures where p-type and n-type transistors are arranged in the vertical dimension rather than lateral arrangement. This three-dimensional configuration increases integration density while using standard CMOS fabrication processes adapted for vertical structures, balancing manufacturing complexity with productivity improvement.
3Area of stationary object
If adjacent transistors share source and drain to reduce area, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The vertically stacked CFET structure shares sources and drains in the vertical dimension, with the first and second transistors sharing common source/drain regions through vertical stacking. This approach reduces planar area while the vertical configuration provides natural isolation that reduces manufacturing precision requirements compared to lateral sharing arrangements.
Data Source
AI summary
A ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored depending on whether first and second local interconnects connected to the nodes of the first transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line. Second data is stored depending on whether third and fourth local interconnects connected to the nodes of the second transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line.