CFET Memory Cell Layout Without Global Word Lines
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Solution Overview
Problem
Existing integrated circuit (IC) devices face challenges in reducing size and complexity, particularly in memory devices used for computing-in-memory (CIM) operations, due to the need for multiplexers and global word lines that increase chip area and noise interference.
Innovation Solution
The IC device incorporates a memory array with local and global bit lines arranged on opposite sides, eliminating the need for multiplexers and global word lines, thereby simplifying circuitry and reducing chip area, while using CFET devices in a stack configuration to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiplexers and global word lines are used in memory devices, then memory functionality is achieved, but chip area increases and noise interference increases
Solution Approach 1:
The memory device is divided into multiple independent memory segments, each with its own local bit lines. This segmentation eliminates the need for global word lines and multiplexers that would otherwise be required to access all memory cells, thereby reducing chip area while maintaining full memory functionality through distributed local access.
Solution Approach 2:
Local bit lines are arranged on opposite sides of the memory array, utilizing the third dimension (vertical stacking) to route signals. This spatial reconfiguration allows direct access to memory cells without requiring global word lines that would consume horizontal chip area, effectively moving the access mechanism from a planar to a立体 architecture.
2Reliability
If multiplexers and global word lines are used in memory devices, then memory functionality is achieved, but noise interference increases
Solution Approach 1:
By dividing the memory into independent segments with local bit lines, the patent isolates noise sources within each segment. This prevents noise from propagating across the entire chip through global word lines, thereby reducing overall noise interference while preserving memory functionality through localized access operations.
Solution Approach 2:
The patent extracts and removes the global word lines and multiplexers from the memory architecture, eliminating the primary sources of noise interference. Memory functionality is maintained through the use of local bit lines that directly access memory cells without requiring the noisy global signaling infrastructure.
3Productivity
If CFET devices in stack configuration are used, then performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
CFET devices are configured in a stack arrangement where transistors are nested vertically one above another, sharing common structures such as source/drain regions. This nesting approach enhances device performance by increasing effective channel width without increasing footprint, while the shared structures reduce manufacturing steps compared to fully discrete transistor fabrication.
Data Source
AI summary
An integrated circuit (IC) device includes a plurality of memory segments. At least one memory segment includes a plurality of memory cells, and a local bit line electrically coupled to the plurality of memory cells and arranged on a first side of the IC device. The IC device further includes a global bit line electrically coupled to the plurality of memory segments, and arranged on a second side of the IC device. The second side is opposite the first side in a thickness direction of the IC device. At least one memory cell in the at least one memory segment includes a complementary field-effect transistor (CFET) device. The CFET device includes a first semiconductor device and a second semiconductor device. The first semiconductor device has a source/drain electrically coupled to the global bit line, and the second semiconductor device has a source/drain electrically coupled to the local bit line.