CFET Memory Power Switch With Diode-Connected Header Stack
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuits (ICs) with complementary field effect transistor (CFET) devices face challenges in optimizing the resistance ratio and chip area utilization in power management switches, particularly in connecting power lines to memory circuits.
Innovation Solution
Implementing a header switch using a CFET device with a first transistor stacked over a second transistor, where the gate terminal of the second transistor is connected to its drain terminal, forming a diode configuration, to improve resistance ratio and reduce chip area by enabling power management based on a power control signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional switch design is used to connect power lines to memory circuits, then the chip area utilization is acceptable, but the resistance ratio between off-resistance and on-resistance is insufficient
Solution Approach 1:
The patent transitions from a planar switch design to a vertically stacked CFET configuration, utilizing the third dimension (vertical stacking) to achieve superior resistance ratio performance without increasing chip area. The stacked arrangement of n-FET and p-FET devices in vertical layers enables enhanced power control while maintaining compact footprint.
Solution Approach 2:
The invention employs complementary field effect transistors (n-FET and p-FET) with opposite electrical characteristics stacked together to form a composite switch device. This composite structure combines the advantages of both transistor types, achieving high on-resistance ratio and effective power management in a single integrated unit.
2Area of stationary object
If the chip area is reduced to improve integration density, then the area utilization improves, but the resistance ratio optimization becomes difficult
Solution Approach 1:
By stacking CFET devices vertically, the patent achieves compact horizontal footprint while maintaining excellent resistance ratio characteristics. The vertical dimension provides the necessary space for resistance optimization without consuming additional chip area, effectively resolving the trade-off between area and performance.
3Reliability
If a stacked CFET configuration is used to improve resistance ratio and reduce area, then the device performance improves, but the device complexity increases
Solution Approach 1:
The patent merges the n-FET and p-FET devices into a single stacked CFET unit, combining multiple functions (power switching, resistance control, area efficiency) into one integrated structure. This merging approach achieves high performance while managing complexity through functional integration rather than separate discrete components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the resistance ratio between off-resistance and on-resistance while minimizing the chip area occupied by the switch, allowing power to be applied to memory circuits on an as-needed basis.
Implementation Method 1
a first transistor (e.g., an n-type field effect transistor (n-FET)) and a second transistor (e.g., a p-type field effect transistor (p-FET)) of the CFET device may be substantially the same or similar
Data Source
AI summary
In an integrated circuit device, a first transistor is stacked with a second transistor, and a third transistor is with a fourth transistor. A gate terminal of the first transistor is configured to receive a control signal. A power line is connected to a source terminal of the first transistor. A drain terminal of the first transistor is connected to both a gate terminal and a drain terminal of the second transistor. A memory power line is connected to a source terminal of the second transistor and a memory circuit is configured to receive a supply voltage from the memory power line. Either the gate terminal and the drain terminal of the third transistor are connected together, or the gate terminal and the drain terminal of the fourth transistor are connected together.