Digital Storage TRIZ Cases

Randomized clock staggering and output binding obscure IMC tile power patterns to protect stationary weight data from side-channel attacks.

A shared resistor and PMOS/NMOS switching layout limits leakage current and reference voltage drop during memory cell activation.

A Ge-Sb-S memory layer with ovonic threshold switching combines selector and storage functions to suppress sneak currents and simplify scaling.

A stacked CFET header switch uses a diode-connected transistor to improve off/on resistance ratio while saving chip area in memory power gating.

By stacking SRAM transistors in the BEOL network, this case increases device density and cuts chip area versus planar layouts.

Local write drivers with NMOS voltage adjustment help SRAM banks overcome bit line leakage and voltage drop during writes.

A stacked SOT-STT MRAM cell uses two free layers and unequal tunnel barriers to deliver four resistance states with compact fabrication.

Coordinated PMOS, NMOS, and offset-cancellation transistors suppress DRAM bit-line noise while stabilizing readout voltages.

Deep trench isolation splits shared-electrode resistive memory wells for independent biasing, reducing leakage and bitcell area.

Stacked neural cores, model memory, and TSV links raise memory capacity and bandwidth while cutting wire length and energy use.

Grouped training across memory pin sets cuts timing storage and training time while maintaining signal integrity and low data skew.

A Ge-Sb-S OTS memory layer combines selector and storage functions to curb sneak currents and support smaller, denser cross-point arrays.

A trench-side phase-change element shares conduction and bit-line regions to cut memory cell area and raise integration density.

A 6T-SRAM CIM circuit uses dual wordlines, a hybrid compressor adder tree, and bit-first accumulation to raise compute and weight density.

Dummy word lines feed reset voltage to bit lines while sense amplifiers are disabled, cutting reset power and latency in row hammer refresh.

Per-rank, per-chipset, and per-DQ ODT tuning improves impedance matching in DRAM and reduces signal reflection in high-capacity memory systems.

Replica sampling and comparator-triggered refresh keep bias voltage accurate while cutting unnecessary current and lab characterization.

Placing speed-critical control circuitry above the memory array cuts footprint, reduces interference, and supports faster, lower-power operation.

A protective film isolates the cross-point cell array from wiring processes, enabling fast low-voltage resistive memory with less process damage.

Sequential ion beam etching and a protective overhang cut MTJ spacing, prevent abnormal connections, and improve reliability.

Auxiliary memory control captures out-of-order stalled data into selected local storage sectors to prevent network stalls and sustain throughput.

Oxide semiconductor channel layers on bit lines cut DRAM leakage in scaled cells, while a trimming insulating block keeps word line contacts flexible.

Stacked tiers of 2-transistor memory cells raise storage density without further cell shrinkage, easing fabrication limits and reducing capacitive coupling.

Replacement counts let the controller shift between normal and target refresh, reducing row-hammer risk, power use, and bus overhead.

Software-calculated ECC lets phase-change memory emulate EEPROM while avoiding hardware ECC rewrites that shorten memory lifetime.

Different SRAM cell architectures tune current drive, leakage, and cell size to match L1, L2, and L3 cache demands.

A hybrid PCM-RRAM bit layout assigns distinct resistance states to MSBs and LSBs to improve memory density without sacrificing accuracy.

Pre-charge and charge-supply circuits boost RRAM sense-node voltage difference, improving read margin at low supply voltage.

Vertically stacked NMOSFETs create parallel read paths in a ROM cell, boosting access speed while avoiding extra gate-signal area.

A shared substrate and parasitic PN junction enable independent RRAM write-read control while shrinking transistor area and spacing waste.

Using two-port or pseudo two-port memory with an ECC cache cuts partial-write latency to one clock cycle and supports back-to-back writes.

Isolation structures and gate-all-around layouts suppress SRAM leakage, improve device matching, and support further cell scaling.

Edge dummy and well strap cells shrink memory-logic spacing, improving fabrication uniformity and circuit performance.

Multiple TSV buses and tCCDBG timing let HBM scale bandwidth while keeping memory array, TSV, and DQ bus timing aligned.

A slow-etch sidewall spacer exposes the MRAM top electrode for strong interconnect contact while limiting MTJ damage and extra masking steps.

Multiple TSV paths and bus switching raise HBM bandwidth while preserving timing synchronization, DQ bus use, and power consumption.

A new tCCDS_SID timing rule lets HBM scale bandwidth across bank groups while keeping memory array, TSV, and DQ bus timing synchronized.

A word line driver and sense amplifier stabilize read voltage in SRAM cells with p-type access transistors, preventing read malfunctions.

Using front-side and back-side fly word lines, this case cuts word line capacitance and delay to speed access at memory-array edges.

Split-current SOT-MRAM cells and a third switch enable faster CiM XOR/XNOR logic without the overhead of larger logic circuits.

Coupling the PDSOI transistor body to a non-gate terminal stabilizes body potential, reducing leakage and threshold drift.

Fluorine-modified substrate chemistry lowers base refractive index to boost VHG diffraction efficiency while preserving monomer solubility.

Shared gate-all-around SRAM gates cut non-functional transistors to shrink multi-port cell area while improving read and write speed.

Shared read-write circuits and power-off array intervals cut MRAM layout area while preserving fast start-up and parallel operations.

Using a hard mask during memory cell etching blocks conductive redeposition on storage-structure sidewalls and prevents electrical shorts.

A GIO booster and latch drive global bit line signals from prior states, cutting LIO charging delay and shortening memory read cycles.

Split even and odd word lines across stacked metal layers with stitch connections to cut resistance and double memory cell pitch efficiency.

Different bit line widths for L1 and L2 SRAM arrays cut parasitic capacitance and voltage drop to improve memory speed and power use.

A perpendicular local amplifier layout between DRAM arrays improves area use and lowers lead-out wire resistance with larger plugs and traces.