Memory Array Word-Line Layout for Lower Resistance and Higher Density
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Solution Overview
Problem
As semiconductor integrated circuits scale down, the increasing resistance and defect rate of access lines in memory devices, particularly word lines, due to the relocation of storage elements as via structures, lead to suboptimal performance and reduced density of memory cells.
Innovation Solution
The solution involves forming source/select lines in the bottommost metallization layer, with even-numbered and odd-numbered word lines in different vertically lower metallization layers, using metal-insulator-metal structures for electrical coupling, and incorporating stitch portions to connect to access transistors, thereby increasing cell density and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If storage elements are relocated as via structures, then device integration is increased, but access line resistance increases and defect rate increases
Solution Approach 1:
The patent distributes word lines across multiple vertically stacked metallization layers (ML1, ML2, ML3) instead of using a single planar layer. This three-dimensional arrangement reduces the lateral distance electrons must travel, thereby reducing resistance while maintaining high integration density through vertical stacking of storage elements and access lines.
Solution Approach 2:
The access line network is segmented into multiple separate metallization layers, with even-numbered word lines in one layer and odd-numbered word lines in another layer. This segmentation allows each layer to be independently optimized and reduces the total resistance by distributing the current path across multiple shorter segments rather than one long lateral path.
2Productivity
If storage elements are relocated as via structures, then production efficiency is increased, but access line defect rate increases
Solution Approach 1:
Different metallization layers are assigned different functions: lower layers (ML1, ML2) contain word lines with stitch portions for transistor coupling, while upper layers (ML3+) contain bit lines and other interconnects. This local differentiation optimizes each layer's performance characteristics and isolates defects to specific layers, preventing cascading failures.
Solution Approach 2:
Stitch portions act as intermediary structures that couple the lower metallization layers containing word lines to the gate structures of access transistors. These stitch portions provide redundant connection paths and isolation, reducing the propagation of defects from the interconnect layer to the transistor layer.
3Quantity of substance
If word lines are placed in higher metallization layers, then storage element density is increased, but access line resistance increases
Solution Approach 1:
The patent utilizes vertical stacking of multiple metallization layers to accommodate both high-density storage elements and low-resistance access lines. By transitioning from a two-dimensional planar layout to a three-dimensional stacked architecture, the system achieves high storage density through vertical placement while maintaining short lateral access line lengths for low resistance.
Solution Approach 2:
Word lines are segmented and distributed across multiple metallization layers (ML1 for even-numbered, ML2 for odd-numbered), with each layer providing partial connectivity. This segmentation reduces the lateral span required in each individual layer, thereby reducing resistance while the collective vertical arrangement maintains high storage element density.
Data Source
AI summary
A memory device includes a memory array comprising a plurality of memory cells arranged over a plurality of rows, the rows including a plurality of word lines, respectively, a first group of the memory cells coupled to an even-numbered one of the word lines and a second group of the memory cells coupled to an odd-numbered one of the word lines. The even-numbered word line is disposed in a first one of a plurality of metallization layers formed vertically above a substrate, wherein the even-numbered word line extends along a first lateral direction and includes a first stitch portion extending in a second lateral direction perpendicular to the first lateral direction. The odd-numbered word line is disposed in a second one of the plurality of metallization layers, wherein the odd-numbered word line extends along the first lateral direction and includes a second stitch portion extending in the second lateral direction.