HBM TSV Bus Switching for Higher Bandwidth at Tight Timing Margins
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Solution Overview
Problem
Existing high bandwidth memory (HBM) devices face challenges in increasing bandwidth while maintaining memory array timing, power consumption, and data synchronization, particularly at tight timing margins, which are exacerbated by higher data rates and increased power consumption.
Innovation Solution
Implementing a timing ratio (tCCDL/tCCDS) and additional TSV data paths to synchronize memory array and TSV bus timings, allowing multiple TSV paths for data transmission, thereby maintaining low power consumption and saturation of the DQ bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rate is increased to enhance bandwidth, then productivity is improved, but power consumption increases and timing margins become tighter
Solution Approach 1:
The patent segments the TSV interconnect structure into multiple independent paths (first TSV path, second TSV path, third TSV path) that can be selectively activated. This segmentation allows the system to distribute data transmission across multiple lower-power paths rather than overloading a single high-speed path, thereby enhancing bandwidth while managing power consumption more effectively.
Solution Approach 2:
The patent implements dynamic selection of TSV paths based on operational requirements. The system can dynamically activate or deactivate specific TSV paths (first, second, or third path) depending on the current bandwidth需求 and power constraints, allowing flexible adaptation between performance and power efficiency.
2Productivity
If multiple TSV paths are added to increase bandwidth, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent divides the TSV interconnect into multiple segmented paths with dedicated select circuits for each path. This segmentation approach, while increasing structural elements, organizes the complexity into manageable, independent units that can be controlled separately, making the overall system more controllable and maintainable despite the increased number of components.
Solution Approach 2:
The patent designs the TSV interconnect structure with universal select circuits that can route data through any of the multiple TSV paths based on operational needs. These select circuits serve multiple functions: path selection, signal routing, and power management, thereby managing complexity through multi-functional components rather than requiring separate dedicated control logic for each path.
3Reliability
If timing synchronization is maintained across multiple TSV paths, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the timing control into path-specific select circuits that independently manage each TSV path. This segmentation allows each path to be timed and controlled separately, ensuring that data arriving through different paths is properly synchronized at the destination without requiring a complex centralized timing controller that would manage all paths simultaneously.
Solution Approach 2:
The patent implements preliminary selection of TSV paths through select circuits before data transmission occurs. By pre-determining which path will carry which data and configuring the select circuits accordingly, the system establishes timing relationships in advance, simplifying the synchronization requirement during actual data transfer operations.
Data Source
AI summary
A system-in-package (SiP) device that includes a base substrate and a processing unit. The SiP also includes a high bandwidth memory (HBM) device that is electrically coupled to the processing unit. The HBM device includes an interface die, which has a bus switching circuit configured to select a through-silicon via (TSV) bus from a plurality of TSV buses, where each TSV bus has a set of TSVs. The bus switching circuit also communicatively couples a DQ bus having a set of DQ pins to the selected TSV bus. The HBM device also includes one or more stacks, with each stack having one or more dies. Each die includes a TSV bus select circuit that communicatively couples a bank group of the die to the TSV bus selected by the bus switching circuit of the interface die. The DQ bus can correspond to a pseudo-channel or channel of the HBM device.