ECC Cache Memory Access for Low-Latency Partial Writes
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Solution Overview
Problem
Existing error-correcting memory systems incur significant latency and inefficiencies due to the need for recalculating error correction codes during partial writes, which require multiple memory accesses and cannot be performed back-to-back.
Innovation Solution
Implementing a pseudo two-port or two-port memory system with an ECC cache that allows simultaneous data retrieval and ECC calculation, enabling back-to-back partial writes and reducing latency by storing updated ECC values temporarily before writing them back to memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are recalculated during partial writes, then data integrity is maintained, but write latency increases and continuous writes cannot be performed
Solution Approach 1:
The patent pre-calculates and stores error correction codes for all possible data word combinations in a lookup table before operation. During partial write operations, the system performs a table lookup instead of recalculating ECC, eliminating the computational delay while maintaining data integrity verification
Solution Approach 2:
The patent prepares multiple sets of error correction codes in advance for different data scenarios. When a partial write occurs, the appropriate pre-prepared ECC set is selected and applied immediately without computation, enabling continuous back-to-back writes while maintaining reliability
2Reliability
If error correction codes are recalculated during partial writes, then data integrity is maintained, but write throughput decreases
Solution Approach 1:
The patent pre-computes error correction codes for all possible data combinations and stores them in lookup tables during manufacturing or initialization. During operation, partial writes simply perform table lookups and apply pre-computed codes, eliminating computational overhead and maximizing write throughput while maintaining data integrity
Solution Approach 2:
The patent creates pre-computed copies of error correction codes for all possible data states. Instead of calculating ECC during writes, the system copies the appropriate pre-computed ECC from lookup tables, dramatically increasing write throughput while ensuring data integrity through verified pre-computed codes
3Reliability
If multiple memory accesses are required for partial writes, then error correction can be performed, but operational efficiency decreases
Solution Approach 1:
The patent pre-organizes error correction codes in lookup tables indexed by data word patterns. During partial writes, the system performs a single table lookup based on the new data pattern and applies the corresponding pre-prepared ECC, reducing multiple memory accesses to a single efficient lookup operation while maintaining full error correction capability
Solution Approach 2:
The patent stores multiple copies of error correction codes in lookup tables organized by data patterns. The system copies the appropriate ECC set from the table in a single operation rather than performing multiple calculate-and-store cycles, improving operational efficiency while preserving error correction functionality
Data Source
AI summary
Described are methods, memory devices, and machine-readable mediums that reduce a partial write latency for error correcting memory systems. The disclosed techniques may utilize either two port, or pseudo two-port memory and an ECC cache to minimize partial-write latency to a single clock cycle. In some examples, on a first clock cycle, the CPU puts partial write data on the bus along with the write address (but does not include an updated ECC). At the same time, the memory device outputs the previous value stored at that address and the previous ECC. At the next clock cycle, the new (updated) ECC is calculated and stored in an ECC cache. During a same clock cycle as the new ECC is being calculated and stored, the previous data integrity (i.e. no ECC errors on the existing data) can be checked and another write, either partial or full, can occur.Micron Confidential