Phase-Change Memory EEPROM Emulation Without Hardware ECC Wear

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Solution Overview

Problem

Existing solutions fail to emulate EEPROM operation in phase-change memory, which is incompatible with flash memory technologies, leading to inefficiencies and reduced memory lifetime due to hardware error correction code recalculations.

Innovation Solution

Implement an EEPROM emulation method in phase-change memory by calculating error correction codes in software, storing data packets and their codes one after the other, and deactivating hardware error correction code storage to optimize memory usage and lifetime.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hardware error correction code storage is activated in phase-change memory, then data integrity is improved, but memory lifetime is reduced due to recalculations

Engineering Contradiction:

Improvedata integrityVSAvoidmemory lifetime

Core Design Contradiction:

ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent extracts the error correction code functionality from hardware and relocates it to software implementation. The hardware error correction code storage zone is deactivated and repurposed for data storage, while software algorithms perform error detection and correction operations, eliminating the harmful recalculations that reduce memory lifetime while maintaining data integrity.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces software as an intermediary between the microprocessor and phase-change memory, mediating error correction operations. Instead of direct hardware recalculations that stress the memory, software routines perform error correction logic, reducing physical wear on the memory cells while preserving reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If phase-change memory is used instead of flash memory for EEPROM emulation, then compatibility with integrated circuits is improved, but existing emulation methods fail to work

Engineering Contradiction:

Improvecompatibility with integrated circuitsVSAvoidemulation functionality

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent changes the operational parameters of phase-change memory to match EEPROM characteristics. By modifying write granularity to byte-level, implementing software-based error correction with specific algorithms, and adjusting memory organization to support EEPROM-like addressing and operations, the phase-change memory achieves EEPROM compatibility while maintaining its inherent advantages for integrated circuit integration.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If error correction codes are calculated and stored for each data packet, then data reliability is improved, but memory space is consumed

Engineering Contradiction:

Improvedata reliabilityVSAvoidmemory space

Core Design Contradiction:

ReliabilityVSVolume of stationary object

Solution Approach 1:

The patent implements partial error correction by applying correction codes selectively based on data packet characteristics and error probability. Rather than universally applying full error correction to all data, the software evaluates data patterns and applies correction only when necessary, reducing the overhead of error correction codes while maintaining reliability for critical data packets.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS12481554B2EEPROM emulation method

Publication Date: 2025.11.25 STMICROELECTRONICS INT NV

AI summary

EEPROM emulation is provided in a phase-change memory of a circuit integrating a microprocessor. A granularity for writing into lines of the phase-change memory is defined according to a size of data packets to be written. A first error correction code calculated by a program executed by said microprocessor is associated with each data packet. Several data packets and their associated first error correction codes are then stored in a same line of the phase-change memory data packet.