Shared-Electrode Resistive Memory Arrays with Independent Well Biasing
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Solution Overview
Problem
Existing resistive memory element structures lack efficient methods for independent biasing and isolation of resistive memory elements, leading to potential reliability issues and increased bitcell area, which affects device performance and scalability.
Innovation Solution
A structure comprising shared top electrodes and independent biasing of isolated well sections, combined with deep trench isolation regions, allows for adaptive body biasing and reduced leakage, enhancing device performance and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If shared top electrodes are used for multiple resistive memory elements, then device area is reduced, but independent biasing capability is lost
Solution Approach 1:
The semiconductor substrate is divided into multiple isolated wells, each serving a specific resistive memory element. This segmentation allows independent biasing control for each memory element while maintaining a shared top electrode structure, thus reducing area while preserving adaptability.
Solution Approach 2:
Isolation regions are introduced as intermediary structures between adjacent wells to prevent electrical interference. These isolation regions enable independent voltage control of each memory element's well while allowing the top electrodes to remain shared, resolving the contradiction between area reduction and independent biasing.
2Reliability
If isolation regions are added to enable independent biasing, then reliability is improved, but device complexity increases
Solution Approach 1:
Multiple functional requirements (isolation, biasing control, and structural support) are merged into a single integrated well structure. The isolated wells serve both as electrical isolation barriers and as independently controllable biasing regions, improving reliability without proportionally increasing complexity.
Solution Approach 2:
The isolated well structure performs multiple functions simultaneously: it provides electrical isolation between adjacent memory elements, enables independent biasing control, and serves as the substrate for transistor formation. This multi-functionality improves reliability while minimizing the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables independent biasing of resistive memory elements, improving device performance by reducing leakage and minimizing bitcell area, while maintaining reliability and scalability.
Implementation Method 1
a plurality of deep trench isolation regions penetrating fully through the dielectric layer and fully through the first well to divide the first well into a plurality of isolated sections
Implementation Method 2
The conductive filaments may be formed, for example, by the diffusion of a conductive species (e.g., metal ions) from one or both of the electrodes into the switching layer
Implementation Method 3
The conductive filaments may be formed, for example, by the diffusion of a conductive species (e.g., metal ions) from one or both of the electrodes into the switching layer
Data Source
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AI summary
Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a first plurality of resistive memory elements including a first plurality of bottom electrodes, a first top electrode, and a first switching layer between the first top electrode and the first plurality of bottom electrodes. The structure further comprises a second plurality of resistive memory elements including a second plurality of bottom electrodes, a second top electrode, and a second switching layer between the second top electrode and the second plurality of bottom electrodes. The first top electrode is shared by the first plurality of resistive memory elements, and the second top electrode is shared by the second plurality of resistive memory elements.