Hybrid PCM-RRAM Memory Array for Bit Density and Accuracy
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Solution Overview
Problem
Conventional memory arrays face issues of degraded density and accuracy due to the use of single-level cell (SLC) or multi-level cell (MLC) structures, where all bits in a word are implemented by either SLCs or MLCs, leading to inefficiencies.
Innovation Solution
Implementing a memory array with a hybrid structure that includes PCM cells with varying levels of Nitrogen doping and RRAM cells, where MSBs use more distinctive resistance levels and LSBs use less distinctive levels, achieved through controlled temperature adjustments and current pulses to manage resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all bits in a word are implemented by SLCs or MLCs uniformly, then the memory structure is simple, but the density and accuracy are degraded
Solution Approach 1:
The patent applies local quality by differentiating the implementation of MSBs and LSBs within the same word. MSBs are implemented using SLC structures for high accuracy, while LSBs are implemented using MLC structures for high density. This allows each bit position to have the appropriate cell structure for its specific requirements, resolving the contradiction between uniform simplicity and differentiated performance.
Solution Approach 2:
The patent segments the N-bit word into two parts: MSBs (most significant bits) and LSBs (least significant bits). Each segment is then implemented with the appropriate cell structure - SLC for MSBs requiring accuracy, and MLC for LSBs where density is more critical. This segmentation allows the system to achieve both high accuracy and high density simultaneously.
2Reliability
If SLC structure is used for all bits, then accuracy is maintained, but memory density is reduced
Solution Approach 1:
The patent applies local quality by assigning SLC structure specifically to MSBs where accuracy is critical, and MLC structure to LSBs where density can be prioritized. This localized differentiation allows the system to maintain high accuracy for significant bits while achieving high density through MLC for less critical bits, resolving the contradiction between uniform accuracy and overall density.
3Quantity of substance
If MLC structure is used for all bits, then memory density is increased, but accuracy is degraded
Solution Approach 1:
The patent applies local quality by using MLC structure for LSBs where density is the primary concern and accuracy requirements are lower, while using SLC structure for MSBs where accuracy is critical. This selective application of MLC to appropriate bit positions allows the system to achieve high overall density without sacrificing the accuracy of significant bits.
Solution Approach 2:
The patent segments the word into MSBs and LSBs, applying different cell structures to each segment. The LSB segment uses MLC for high density, while the MSB segment uses SLC for high accuracy. This segmentation strategy resolves the contradiction by allowing MLC to be used extensively for density while protecting accuracy through SLC in critical positions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances memory density and accuracy by optimizing resistance states for MSBs and LSBs, allowing for precise data storage with higher bit capacity and reliability.
Implementation Method 1
a first phase change memory (PCM) cell, in which a material of the first PCM cell includes a phase change material
Implementation Method 2
a second PCM cell, in which a material of the second PCM cell includes a resistive random access memory (RRAM) material
Data Source
AI summary
The disclosure provides a memory device, a memory array, and an N-bit memory unit. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.