Cross-Point Resistive Memory Layout With Protective Film Isolation

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Solution Overview

Problem

There is a need for high-performance memory devices with rapid operation and low operating voltage as electronic devices become increasingly integrated, and existing variable resistance memory devices have not adequately addressed this requirement.

Innovation Solution

A variable resistance memory device is designed with a substrate, a cell array region containing memory cells, a wiring region with an inter-wiring insulating film, and a protective film, featuring conductive lines and memory cells arranged at intersections, along with specific materials and structures for the switching and variable resistance patterns to enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a protective film is added between the cell array region and wiring region, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveprotection from process-related damagesVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A protective film is introduced as an intermediary layer between the cell array region and the wiring region. This film serves as a mediator that prevents direct contact and potential damage from fabrication processes, while allowing the device to maintain its functional integrity without requiring complex protective structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs a thin protective film that conformally covers the cell array region. This thin-film approach provides effective protection against process-related damages while minimizing the added complexity and maintaining a compact device structure.

Inventive Principle:
Principle #30Flexible shells and thin films

2Productivity

If memory cells are arranged at intersections of conductive lines, then productivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveinformation storage efficiencyVSAvoidalignment precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The device is segmented into a cell array region with memory cells arranged at intersections, and a separate wiring region with conductive lines. This segmentation allows for simplified manufacturing processes where the cell array can be formed first with standard alignment, and the wiring region can be added subsequently without requiring ultra-precise alignment between the two regions, thus maintaining high productivity while reducing precision requirements.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The device achieves rapid operation and low voltage requirements, providing efficient information storage through phase change and threshold switching mechanisms, while protecting the cell array from process-related damages.

Implementation Method 1

each of the memory cells includes a switching pattern and a variable resistance pattern

Methodology Applied
Scientific EffectPhase change: Phase Change

Implementation Method 2

each of the memory cells includes a switching pattern and a variable resistance pattern

Methodology Applied
Scientific EffectThreshold switching:

Data Source

PatentUS12484233B2Variable resistance memory device
Publication Date: 2025.11.25 SAMSUNG ELECTRONICS CO LTD
  • US12484233B2 patent drawing
  • US12484233B2 patent drawing
  • US12484233B2 patent drawing

AI summary

A variable resistance memory device includes a substrate, a cell array region including a plurality of memory cells on the substrate, a wiring region which includes an inter-wiring insulating film stacked on the cell array region, and an upper wiring structure in the inter-wiring insulating film and a protective film which covers an upper surface of the cell array region, between the cell array region and the wiring region, wherein each of the memory cells includes a switching pattern and a variable resistance pattern, the cell array region further includes first conductive lines extending in a first direction, and a second conductive lines extending in a second direction intersecting the first direction, and the plurality of memory cells are disposed at an intersections of the first conductive lines and the second conductive lines.