IMC Tile Clock Staggering for Side-Channel Resistance
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Solution Overview
Problem
In-memory computation processing systems are vulnerable to side channel attacks, particularly when computational weight data remains stationary and exhibits sparsity, making it susceptible to unauthorized extraction.
Innovation Solution
Implement a randomized clock staggering and output binding mechanism in the in-memory computation processing tiles, using a clock tree to apply a randomized stagger to clock signals and a binding circuit to account for timing offsets, thereby randomizing power patterns and making it difficult to discern computational weight data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If computational weight data remains stationary and exhibits sparsity for efficient in-memory computation, then computation performance is improved, but vulnerability to side channel attacks increases
Solution Approach 1:
The patent applies dynamics by introducing randomized clock staggering that varies the timing of clock signals dynamically across different processing tiles. This creates temporal variability in power consumption patterns while maintaining the stationary nature of weight data in memory, thus preserving computation performance while disrupting side channel attack patterns
Solution Approach 2:
The patent changes the timing parameter of clock signals by applying randomized staggers to different processing tiles. This parameter change creates variability in when operations are executed without changing the fundamental computation logic, thereby altering power consumption patterns to prevent successful side channel attacks while maintaining computational correctness through binding circuits
2Reliability
If randomized clock staggering is applied to protect against side channel attacks, then security is improved, but timing synchronization complexity increases
Solution Approach 1:
The patent introduces binding circuits as intermediary components that receive outputs from multiple processing tiles with randomized timing and reorder them according to the same random stagger pattern. This mediator approach simplifies the synchronization complexity by providing a deterministic reordering mechanism that compensates for the randomized timing, maintaining security while managing complexity
Data Source
AI summary
First and second in-memory computation (IMC) processing tiles store computational weight data for in-memory computation operations executed in response to feature data. The first IMC processing tile is clocked by a first clock signal to control execution of the in-memory computation operation, and the second IMC processing tile is clocked by a second clock signal to control execution of the in-memory computation operation. A clock tree generates the first and second clock signals. In response to a random number, the clock tree applies a randomized stagger to timing of the first and second clock signals. A binding circuit matches and binds the first and second computation outputs. The binding circuit, in response to the random number, accounts for timing offset between the first and second computation outputs due to the randomized stagger to timing of the first and second clock signals.