MRAM Top Electrode Spacer Structure for MTJ-Safe Contact Etching
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Solution Overview
Problem
The formation of MRAM devices is challenged by high power etch processes that can damage the magnetic tunnel junction (MTJ) during the exposure of the top electrode, leading to electrical shorting or poor connections, and the use of multiple masking layers increases time and costs.
Innovation Solution
A simplified method involving a protective sidewall spacer layer etched at a slower rate than the upper ILD structure is used to expose the top electrode, allowing a strong electrical connection without damaging the MTJ, and reducing the number of etch processes and masking layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high power etch processes are used to expose the top electrode, then the top electrode can be effectively exposed, but the magnetic tunnel junction (MTJ) is damaged leading to electrical shorting or poor connections
Solution Approach 1:
The patent divides the etch process into multiple stages with different power levels. A first etch process uses high power to remove the upper inter-level dielectric layer, while a second etch process uses reduced power to expose the top electrode without damaging the MTJ. This segmentation allows each stage to be optimized for its specific purpose, resolving the contradiction between effective exposure and MTJ protection.
Solution Approach 2:
The patent performs preliminary removal of the upper inter-level dielectric layer before exposing the top electrode. By removing the dielectric material first, the subsequent etch process only needs to expose the top electrode rather than removing both dielectric and electrode, allowing for lower power settings that protect the MTJ while still achieving effective exposure.
2Manufacturing precision
If multiple masking layers are used in the etch process, then the etching can be more precise and controlled, but the fabrication time and costs increase
Solution Approach 1:
The patent combines multiple etch operations into a single etch process by using a single masking layer that defines both the contact hole pattern and the top electrode exposure pattern. This merging eliminates the need for separate masking and etching steps, reducing fabrication time and costs while maintaining etching precision through careful masking layer design.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip including a memory cell over a substrate and comprising a first electrode over a data storage structure. A first spacer layer is on opposing sidewalls of the memory cell. A second spacer layer is around the first spacer layer. The second spacer layer extends along a top surface of the first spacer layer and abuts the first electrode. The second spacer layer has a top surface aligned with or below a top surface of the first electrode. A conductive interconnect overlies the memory cell and contacts the top surface of the second spacer layer and the first electrode.