DRAM Local Amplifier Layout for Higher Density and Lower Resistance
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Solution Overview
Problem
Current memory layout designs suffer from insufficient utilization of layout area and unreasonable arrangement of devices, affecting the performance and size of dynamic random access memory (DRAM) devices.
Innovation Solution
The memory layout includes multiple memory arrays arranged in a preset direction with local amplifiers between adjacent arrays, featuring transistors perpendicular to the direction, aligned or staggered conductive plugs, and conductive layers with independent traces to enhance transistor density and conductive plug size, allowing for improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are arranged parallel to the preset direction in conventional memory layouts, then the layout area utilization is insufficient and device arrangement is unreasonable, but changing the arrangement direction to perpendicular to the preset direction increases transistor density and layout efficiency
Solution Approach 1:
The patent changes the arrangement direction of transistors from parallel to perpendicular relative to the preset direction, effectively utilizing the vertical dimension of the layout space. This dimensional reorientation allows for denser packing of transistors and improved layout area utilization without increasing horizontal footprint.
2Reliability
If conventional memory layouts are used, then the on-resistance of lead-out wires is high, but by increasing the size of conductive plugs and traces, the on-resistance is reduced and electrical performance is enhanced
Solution Approach 1:
The patent modifies the physical parameters of conductive plugs and traces by increasing their dimensions (length, width, or cross-sectional area). This parameter change directly reduces the on-resistance of the lead-out wires, thereby improving electrical performance and signal integrity in the memory device.
Data Source
AI summary
A memory layout is disclosed. The memory layout includes multiple memory arrays arranged in a preset direction and a local amplifier located between adjacent memory arrays. The local amplifier is configured to implement data transmission between a local data line and a global data line. The local amplifier includes multiple transistors arranged perpendicular to the preset direction, where the multiple transistors have a common active region, each of the multiple transistors has a corresponding gate structure, the multiple gate structures are located in the active region and arranged at intervals perpendicular to the preset direction, and the gate structures extend in the preset direction. The local amplifier further includes multiple conductive plugs located in the active region and disposed at intervals from the gate structures, where the conductive plugs extend in the preset direction.