CFET ROM Memory Cell Layout for Faster Read Paths
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Solution Overview
Problem
Read-Only Memory (ROM) devices using one N-typed Metal-Oxide-Semiconductor Field Transistor (NMOSFET) are limited by speed and occupy a large area due to separate gate signals.
Innovation Solution
Implementing a memory cell structure with a complementary Field Effect Transistor (CFET) configuration, where two N-typed FETs are vertically arranged with gates on different layers, enhancing the reading path with parallel transistors to improve speed and reduce area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If one NMOSFET is used as the ROM cell, then the device complexity is reduced, but the speed is limited
Solution Approach 1:
The patent transitions from a planar single-transistor configuration to a three-dimensional stacked configuration with two NMOSFETs arranged vertically. The gates are positioned on different layers (first gate on first layer, second gate on second layer), enabling simultaneous operation along the vertical dimension while maintaining compact footprint. This dimensional change allows parallel signal paths without increasing lateral area, thereby improving speed while managing complexity through vertical integration.
2Speed
If two separated gate signals are used, then the reading path is enhanced, but the area increases
Solution Approach 1:
The patent resolves the area-speed contradiction by stacking two NMOSFETs vertically with their gates on different layers. This vertical arrangement creates parallel reading paths for enhanced speed while maintaining a compact lateral footprint. The first NMOSFET and second NMOSFET share the same lateral space but operate on different vertical layers, enabling simultaneous signal processing without area expansion.
Solution Approach 2:
The patent merges two NMOSFET functions into a single compact cell structure. Both transistors are integrated within the same ROM cell footprint, sharing common diffusion regions and interconnect structures. This merging approach enables parallel gate signal operation while consolidating the physical layout, thereby achieving enhanced reading path speed without proportionally increasing the total cell area.
Data Source
AI summary
A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.