6T-SRAM CIM Circuit With Flexible Input and Hybrid Adder Tree
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Solution Overview
Problem
Existing digital compute-in-memory (DCIM) systems face a trade-off between weight density and compute density, with reduced weight density due to large arithmetic hardware and limited energy efficiency improvements.
Innovation Solution
A 6T-SRAM-based CIM device employs a static dual wordline access scheme, hybrid compressor adder-tree, and bit-first accumulation to optimize weight and compute density, using area-efficient transmission-gate full adders and half adders, and bi-directional shifters to reduce switching activities and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large amount of arithmetic hardware is employed in DCIM, then compute density (TOPS/mm2) is improved, but weight density (Kb/mm2) is reduced
Solution Approach 1:
The SRAM array is divided into multiple column structures, each containing sub-column structures with bitcells. This segmentation allows the system to process multiple input bits simultaneously through parallel column operations, improving compute density without proportionally increasing the area occupied by arithmetic hardware.
Solution Approach 2:
The patent introduces a multi-dimensional processing approach by organizing bitcells in 8 sub-columns that can be selectively activated. By controlling wordlines to access different combinations of bitcells across sub-columns, the system achieves higher compute density through spatial multiplexing without linearly increasing hardware area.
2Quantity of substance
If time-sharing/reusing arithmetic hardware across inputs and weights is used, then weight density (Kb/mm2) is improved, but compute density (TOPS/mm2) is degraded
Solution Approach 1:
The system pre-charges selected bitcells in the SRAM array before the actual computation occurs. By preparing the data in advance and organizing it across multiple sub-columns, the system enables parallel processing operations that achieve high compute density without requiring extensive time-sharing of arithmetic hardware.
Solution Approach 2:
The patent maintains continuous useful action by enabling simultaneous operations across multiple column structures. While some columns perform multiplication operations, others can be prepared or transferred data, ensuring that the arithmetic hardware remains continuously utilized without idle time-sharing transitions, thereby maintaining high compute density.
3Use of energy by moving object
If static dual wordline access without pre-charging is used, then energy efficiency (TOPS/W) is improved, but manufacturing precision requirements increase
Solution Approach 1:
The system dynamically controls wordline activation to select specific bitcells for access. By selectively enabling wordlines that correspond to desired input bits and using control logic to manage the dual wordline access, the system achieves precise bitcell selection without requiring pre-charging operations, thereby improving energy efficiency while maintaining access precision through dynamic control.
Data Source
AI summary
Compute-in-memory (CIM) devices and methods for performing vector-matrix multiplication (VMM) are provided. The disclosed CIM device can include a static random access memory (SRAM) array. The SRAM array can include a plurality of column structures. Each column structure can include eight sub-column structures. Each sub-column structure can include at least one bitcell sharing a pair of a local bitline (LBL) and LBLb that can be connected to a pair of global bitlines (GBL) via switches. Each sub-column comprises at least one NOR gate. An even-numbered bitcell can include a wordline 1 (WL1) for a left access transistors, and an odd-numbered bitcell can include a wordline 2 (WL2) for a right access transistors. Every eight columns (8 columns) can be configured to share a hybrid compressor adder-tree (HCA), followed by a bit-first accumulation (BFA).