Sense Amplifier Offset Cancellation for Stable DRAM Readout
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Solution Overview
Problem
The offset noise in dynamic random access memory (DRAM) due to varying device characteristics causes voltage fluctuations in the bit lines, reducing readout accuracy and performance.
Innovation Solution
A sense amplification circuit with specific transistor configurations and control signals to stabilize the bit line voltages, including PMOS and NMOS transistors, and offset cancellation MOS transistors to cancel noise while avoiding voltage fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the bit line is electrically connected to a complementary readout bit line and the complementary bit line is electrically connected to a readout bit line to cancel offset noise, then the offset noise is reduced, but voltage fluctuations of the readout bit line and complementary readout bit line occur, reducing readout accuracy
Solution Approach 1:
The patent divides the sense amplification circuit into multiple independent transistor groups (first PMOS, second PMOS, first NMOS, second NMOS) with separate control mechanisms. Each transistor group can be independently controlled through dedicated control signals, allowing precise regulation of voltage fluctuations while maintaining offset cancellation benefits. This segmentation enables fine-grained control over the amplification process without the voltage instability caused by unified control.
Solution Approach 2:
The patent dynamically adjusts the threshold voltages of transistors by applying specific control signals (first control signal, second control signal, third control signal, fourth control signal) to respective transistors. This parameter change approach allows the circuit to adapt transistor characteristics in real-time, compensating for voltage fluctuations on readout bit lines while maintaining effective offset noise cancellation through coordinated transistor operation.
2Power
If PMOS transistors are used in the sense amplification circuit to amplify voltage differences, then the amplification capability is improved, but device characteristic variations due to process and temperature cause offset noise
Solution Approach 1:
The patent employs asymmetric transistor pairing where first PMOS and second PMOS transistors have different control mechanisms, as do first NMOS and second NMOS transistors. This asymmetric control allows each transistor to be optimized for its specific operating conditions, compensating for process and temperature variations. The differential configuration with independent control creates an asymmetric balance that cancels offset noise while preserving amplification capability.
Solution Approach 2:
The circuit implements feedback through the control signal mechanism where the operation of one transistor group influences the control of another. The control signals are generated based on the detected voltage differences and feed back to adjust transistor threshold voltages, creating a self-correcting system that maintains amplification capability while dynamically compensating for offset noise caused by device characteristic variations.
Data Source
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AI summary
The present disclosure provides a sense amplification circuit and a method of reading out data, including: a first PMOS transistor; a first NMOS transistor; a second PMOS transistor; a second NMOS transistor; a first control MOS transistor configured to provide a bias voltage to the first PMOS transistor according to a control signal; a second control MOS transistor configured to provide the bias voltage to the second PMOS transistor according to the control signal; a first offset cancellation MOS transistor configured to electrically connect an initial bit line to a first complementary readout bit line according to an offset cancellation signal; and a second offset cancellation MOS transistor configured to electrically connect an initial complementary bit line to a first readout bit line according to the offset cancellation signal.