3D Stacked SRAM Cell Structure for Higher BEOL Density
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Solution Overview
Problem
Existing SRAM cell implementations are limited by device density, which restricts chip area and increases fabrication costs due to planar surface area constraints.
Innovation Solution
The SRAM cells are formed in a back-end-of-line (BEOL) network, allowing transistors to be stacked rather than planar, reducing chip area requirements and lowering fabrication costs while providing design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If SRAM cells are implemented using planar configuration, then manufacturing process is simple, but device density is limited and chip area increases
Solution Approach 1:
The patent transitions from planar (2D) SRAM cell configuration to three-dimensional (3D) stacked configuration by forming transistors in multiple vertical layers. This dimensional change allows multiple transistor stacks to occupy the same footprint area, thereby increasing device density without proportionally increasing chip area. The vertical stacking is achieved through sequential deposition of channel layers, gate dielectric, and gate electrodes in different vertical positions.
2Quantity of substance
If SRAM cells are implemented using planar configuration, then fabrication cost is higher due to increased chip area, but 3D stacking increases manufacturing complexity
Solution Approach 1:
The SRAM cell is divided into multiple independent transistor stacks arranged in vertical layers. Each stack consists of a channel layer, gate dielectric, and gate electrode formed in a specific vertical position. This segmentation allows each component to be fabricated using dedicated processes optimized for its layer, while the overall structure achieves compact footprint. The crosscoupled inverter structure is segmented into separate transistor stacks that can be independently controlled.
Solution Approach 2:
The patent implements nesting by placing transistor stacks within the same footprint area at different vertical levels. Multiple transistor stacks are nested in the vertical dimension, with upper stacks positioned above lower stacks. This nesting approach allows the SRAM cell to fit within a smaller chip area compared to planar configurations, as the vertical space is utilized efficiently to accommodate all necessary transistors.
3Quantity of substance
If transistors are stacked in 3D configuration, then device density increases and chip area reduces, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming the gate dielectric layer and gate electrode structures in predetermined vertical positions before depositing subsequent channel layers. The gate structures are prepared in advance at specific heights, and then channel layers are deposited in sequential vertical steps. This preliminary preparation ensures proper vertical alignment and reduces the precision requirements during later fabrication steps, as the alignment references are already in place.
Data Source
AI summary
An SRAM cell includes a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device; a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the first direction; and a fourth n-channel layer engaged with a fourth gate layer to form a sixth device, the fourth gate layer coupled to a second word line and the fourth n-channel layer coupled to the third n-channel layer along the second direction.