Dummy Word Line Memory Reset for Row Hammer Refresh

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Memory devices are vulnerable to row hammer attacks, which cause unintended changes in nearby memory cells due to frequent activation of a same row, leading to inaccurate refresh operations, increased power consumption, and reduced mitigation effectiveness.

Innovation Solution

The use of dummy word lines to perform reset operations on memory cells by coupling bit lines with a voltage node and disabling sense amplifiers during the reset process, reducing power consumption and improving the accuracy and efficiency of refresh operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If traditional reset operations are used without dummy word lines, then memory cells can be reset, but power consumption is high and reset operation complexity is increased

Engineering Contradiction:
Improvepower consumptionVSAvoidreset operation complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent introduces dummy word lines as intermediary elements between the actual word lines and the bit lines. These dummy word lines serve as mediators to perform the reset operation by coupling bit lines with voltage nodes, thereby reducing the complexity and power consumption of the traditional reset operation without requiring sense amplifiers

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the word line function into two distinct components: actual word lines for normal memory access operations and dummy word lines specifically for reset operations. This segmentation allows the reset function to be performed independently with reduced complexity and lower power consumption

Inventive Principle:
Principle #1Segmentation

2Loss of time

If sense amplifiers are enabled during reset operations, then memory cells can be reset, but operation latency is increased

Engineering Contradiction:
Improvereset operation latencyVSAvoidreset operation reliability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent extracts the sense amplifier component from the reset operation pathway. By using dummy word lines to directly couple bit lines with voltage nodes, the sense amplifiers are taken out of the critical reset signal path, eliminating their contribution to operation latency while maintaining reset reliability through the direct voltage coupling mechanism

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If row hammer attacks occur, then frequent word line activations happen, but this leads to inaccurate refresh operations and reduced mitigation effectiveness

Engineering Contradiction:
Improverow hammer mitigation effectivenessVSAvoidrefresh operation accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The dummy word lines act as intermediaries that enable accurate tracking of word line activation frequencies. By providing dedicated reset pathways, they facilitate precise measurement of access patterns, which is critical for detecting row hammer attacks and performing accurate refresh operations

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12482511B2Techniques for memory cell reset using dummy word lines
Publication Date: 2025.11.25 MICRON TECHNOLOGY INC
  • US12482511B2 patent drawing
  • US12482511B2 patent drawing
  • US12482511B2 patent drawing

AI summary

Methods, systems, and devices for techniques for memory cell reset using dummy word lines are described. A memory device may activate, as part of a reset operation, one or more dummy word lines to couple a voltage node with a bit line to supply the bit line with a reset voltage supplied to the voltage node. The memory device may then activate one or more word lines to couple the bit line with one or more memory cells to supply the one or more memory cells with the reset voltage such that the one or more memory cells are reset. In some cases, the memory device may disable one or more components of a sense amplifier coupled with the bit line during the reset operation to support the voltage node supplying the bit line with the reset voltage.