SRAM Read Circuit Using P-Type Access Transistors
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Solution Overview
Problem
Conventional semiconductor storage devices using p-type transistors for access transistors in SRAM cells lack a detailed disclosure of the peripheral circuit, particularly the read circuit, which can lead to malfunctions due to voltage drops during data read operations.
Innovation Solution
A semiconductor storage device is designed with a specific configuration of p-type and n-type transistors forming memory cells and sense amplifiers, along with a word line driver that uses clock and address signals to manage word lines, ensuring stable data read operations by maintaining optimal voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a p-type transistor is used for the access transistor in an SRAM cell, then the SRAM cell can be formed with specific transistor configurations, but voltage drops occur during data read operations causing malfunctions
Solution Approach 1:
The word line driver circuit is activated before the access transistor to pre-charge the word line to a high level, ensuring that sufficient voltage is available across the access transistor during the subsequent read operation. This preliminary action prevents voltage drops that would otherwise cause malfunctions.
Solution Approach 2:
The patent changes the voltage parameter of the word line by using a word line driver circuit that can output high voltage levels. This parameter change ensures that the access transistor receives adequate voltage during read operations, preventing voltage drops and associated malfunctions.
2Device complexity
If conventional SRAM cell configuration is used without detailed peripheral circuits, then the design is simpler, but malfunctions occur due to insufficient voltage control during read operations
Solution Approach 1:
The peripheral circuit is segmented into distinct functional blocks: a word line driver circuit for voltage control, a sense amplifier circuit for signal detection, and an output circuit for data transmission. This segmentation allows each component to perform its specific function optimally while maintaining overall system reliability.
Solution Approach 2:
The word line driver circuit acts as an intermediary between the control signals and the access transistor, providing the necessary voltage levels to ensure reliable operation. This intermediary component bridges the gap between simple SRAM cell configuration and reliable read operations.
3Adaptability or versatility
If p-type transistors are used for access transistors, then transistor resistance varies during operation, but this variation causes voltage drops and operational failures
Solution Approach 1:
The sense amplifier circuit provides feedback to monitor the voltage levels and signal states during read operations. This feedback mechanism allows the circuit to detect and compensate for voltage drops caused by transistor resistance variations, maintaining stable operation.
Solution Approach 2:
The word line driver circuit performs preliminary voltage establishment before the read operation begins, ensuring that the access transistor is properly biased. This preliminary action compensates for subsequent resistance variations by maintaining adequate voltage headroom throughout the operation.
Data Source
AI summary
A semiconductor storage device includes memory cells and a sense amplifier circuit. Each of the memory cells includes p-type drive transistors, n-type load transistors, and p-type access transistors connected to a bit line pair. The sense amplifier circuit includes p-type transistors and n-type transistors.