HBM Command Timing for Higher Bandwidth Across Bank Groups
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Solution Overview
Problem
Existing vertically stacked high bandwidth memory devices face challenges in increasing bandwidth without altering memory array timing or reducing the number of addressable bank groups, as higher data rates lead to unsynchronized memory array, TSV bus, and DQ bus timings.
Innovation Solution
Implementing a 4N architecture with increased bank groups per channel, extending tCCDL CLK cycle periods, introducing a new timing parameter tCCDS_SID for commands to different bank groups in the same stack, and optimizing transmit/receive circuits to maintain synchronization and saturation of the DQ bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher data rates are implemented to increase bandwidth, then bandwidth is improved, but memory array, TSV bus, and DQ bus timings become unsynchronized
Solution Approach 1:
The patent implements dynamic timing adjustments by introducing a 4N architecture where the tCCDL clock cycle period is extended and a new timing parameter tCCDS_SID is added. This allows the timing relationships between memory array, TSV bus, and DQ bus to be dynamically adjusted to maintain synchronization at higher data rates, resolving the contradiction between increased bandwidth and timing synchronization reliability.
Solution Approach 2:
The patent changes key timing parameters including extending the tCCDL clock cycle period and introducing the tCCDS_SID parameter for commands to different bank groups. These parameter changes enable the system to maintain proper timing synchronization while operating at higher data rates, thus improving bandwidth without sacrificing reliability.
2Productivity
If the number of bank groups is increased to improve bandwidth, then bandwidth is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by organizing memory into multiple bank groups within a 4N architecture, where N represents the number of banks per bank group. This segmentation allows increased bandwidth through parallel access to multiple bank groups while managing complexity through structured organization and standardized timing parameters like tCCDS_SID for inter-bank-group command scheduling.
3Productivity
If memory array timing is altered to increase bandwidth, then bandwidth is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements preliminary action by pre-defining standardized timing parameters (tCCDL extension, tCCDS_SID) that establish proper synchronization relationships before operation. This preliminary timing setup allows the system to achieve high bandwidth without requiring complex real-time timing adjustments, thereby reducing manufacturing precision requirements while maintaining performance.
Data Source
AI summary
A system-in-package (SiP) device can include a base substrate and a processing unit. The SiP can also include a high bandwidth memory (HBM) device electrically coupled to the processing unit. The HBM device can also include a plurality of stacks, with each stack having a plurality of bank groups associated with a same channel or pseudo-channel. Based on a timing parameter communicated from the HBM device, the processing unit can be configured to transmit a first command to a first bank group associated with a first stack and configured to transmit a second command to a second bank group associated with the first stack no less than tCCDS_SID clock (CLK) cycles after transmitting the first command. The tCCDS_SID is a ratio of tCCDL/tCCDS and is greater than 2.