Global Bit Line Boosting for Faster Memory Signal Latching
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Solution Overview
Problem
Memory devices with multiple memory banks experience significant time delays in signal transmission due to increased distance between local and global input/output circuits, necessitating prolonged charging times for signals to be latched, which delays data access.
Innovation Solution
Implementing a booster circuit and latch circuit within the global input/output circuit to drive and latch signals independently of local circuit charging, reducing dependency on local circuit charging times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between LIO circuit and GIO circuit is increased to accommodate multiple memory banks, then the memory device can store more data, but the signal transmission time delay increases
Solution Approach 1:
The patent segments the signal transmission path by introducing intermediate boosting circuits at strategic points between LIO and GIO circuits. This divides the long transmission path into shorter segments, each with its own boosting circuit that refreshes the signal, thereby reducing cumulative transmission delay while maintaining the physical separation needed for multiple memory banks
Solution Approach 2:
The patent introduces boosting circuits as intermediary elements between LIO and GIO circuits. These intermediary circuits actively refresh and reinforce signals during transmission, compensating for the increased distance and reducing time delay without requiring the LIO and GIO circuits to be physically closer
2Reliability
If the charging time of signals in LIO circuit is prolonged to ensure signals are latched in GIO circuit, then signal latching reliability is improved, but data access time increases
Solution Approach 1:
The patent applies preliminary action by pre-charging and pre-boosting signals in the LIO circuit and intermediate boosting circuits before the signals reach the GIO circuit. This preliminary reinforcement ensures that signals arrive at the GIO circuit with sufficient strength for reliable latching, eliminating the need for prolonged charging times
Solution Approach 2:
The patent replaces the passive mechanical charging process with active electronic boosting circuits. Instead of relying solely on capacitive charging over time, voltage-boosting circuits actively amplify and refresh signals, providing reliable latching without requiring extended charging durations
3Device complexity
If the dependency of latching signals in GIO circuit on charging signals in LIO circuit is maintained, then circuit design is simplified, but access time is increased
Solution Approach 1:
The patent segments the signal processing function by separating charging (performed in LIO circuit) from boosting (performed in intermediate circuits and GIO circuit). This segmentation allows each circuit to perform its specialized function efficiently, reducing access time while maintaining manageable complexity through modular design
Data Source
AI summary
Systems and methods are provided for a memory device including a first memory array, a local input/output (LIO) circuit, and a global input/output (GIO) circuit. The first memory array includes a memory cell and a local bit line. The LIO circuit is configured to receive a local bit line signal on the local bit line and to generate a global bit line signal on a global bit line based on the local bit line signal. The GIO circuit is coupled to the LIO circuit and is configured to receive the global bit line signal. The GIO circuit comprises a latch circuit including a global bit line signal latch that is configured to latch the global bit line signal, and a booster circuit that is configured to drive the global bit line signal in the GIO circuit based on a previous global bit line signal.