RRAM Memory Cell Layout Using Shared Substrate Write Bias
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Solution Overview
Problem
The storage density and performance of mainstream flash memory are limited by physical laws, making it difficult to meet the increasing demand for non-transitory memory in fields such as big data, Internet of Things, and cloud computing.
Innovation Solution
A memory cell design utilizing a first and second transistor connected in series, with independent control through bit and word lines, and a shared substrate for parasitic PN junction biasing, allowing for independent data writing and reading in resistive random-access memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory structure is used, then storage capacity can be achieved, but storage density is limited by physical laws and transistor area
Solution Approach 1:
The patent merges the write control function into the substrate of the second transistor by forming a parasitic PN junction, eliminating the need for a separate write word line. This consolidation reduces the overall transistor area while maintaining the dual-transistor series configuration needed for memory operation, directly addressing the contradiction between storage density and transistor area.
Solution Approach 2:
The substrate of the second transistor serves multiple functions: it acts as both the substrate for the transistor structure and as the write control electrode through the parasitic PN junction. This multi-functionality reduces the number of separate components needed, thereby reducing transistor area while maintaining storage capacity.
2Adaptability or versatility
If independent write control is implemented, then data writing flexibility is improved, but additional word lines increase device complexity
Solution Approach 1:
The patent extracts the write control function from a separate word line structure and integrates it into the substrate of the second transistor through a parasitic PN junction. This extraction eliminates the need for an additional write word line, reducing device complexity while preserving independent write control capability through the PN junction biasing mechanism.
3Quantity of substance
If transistor spacing is reduced, then storage density increases, but spacing waste between transistors becomes more significant
Solution Approach 1:
By merging the write control function into the substrate and eliminating the need for a separate write word line and associated spacing, the patent reduces the spacing waste between transistors. The shared substrate structure allows transistors to be placed closer together, increasing storage density while minimizing the spacing waste that would otherwise be required for independent write control structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces transistor area and minimizes spacing waste, enhancing storage density and performance by enabling efficient data processing and reducing the size of memory cells.
Implementation Method 1
a parasitic PN junction in the substrate of the first transistor and a parasitic PN junction in the substrate of the second transistor are turned on to write first data to the first memory device and the second memory device
Data Source
AI summary
The present disclosure relates to a memory cell, a memory array, an electronic device and a data processing method. The memory cell includes a first transistor and a second transistor. A first terminal of the first transistor is configured to be electrically connected to a first bit line through a first memory device, a second terminal of the first transistor is configured to be electrically connected to a source line, and a control terminal of the first transistor is configured to be electrically connected to a first word line. A first terminal of the second transistor is configured to be electrically connected to a second bit line through a second memory device, a second terminal of the second transistor is configured to be electrically connected to the first terminal of the first transistor, a control terminal of the second transistor is configured to be electrically connected to a second word line, and a substrate of the second transistor is configured to be electrically connected to a substrate of the first transistor and a write source line.