Memory Pin Group Training for Lower Data Interface Overhead
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Solution Overview
Problem
Training memory devices with multiple data pins is resource-intensive and time-consuming, as each pin requires individual training, which increases the overall training time and resource utilization.
Innovation Solution
The memory device performs training for multiple data pins by grouping them, determining and storing transmission and receiving timing for each group, rather than individual pins, thereby reducing the need to store timing information for each pin separately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If training is performed for each data pin individually, then signal integrity and data transmission reliability are improved, but training time and training resources increase significantly
Solution Approach 1:
The patent merges multiple data pins into groups (e.g., first data pins and second data pins) and performs training operations on each group collectively rather than on individual pins. This combining approach maintains signal integrity requirements while significantly reducing training time and resource consumption by processing multiple pins simultaneously through grouped training operations.
2Reliability
If training is performed for each data pin individually, then signal integrity and data transmission reliability are improved, but training resources (storage and processing) increase significantly
Solution Approach 1:
The patent combines multiple data pins into groups and performs unified training operations on each group, reducing the number of separate training processes required. This merging strategy maintains the reliability benefits of individual pin training while reducing overall training resource consumption through consolidated processing and storage requirements.
Solution Approach 2:
The patent segments data pins into distinct groups (first data pins and second data pins) with different training characteristics, allowing optimized training strategies for each segment. This segmentation enables tailored training approaches that reduce overall resource consumption while maintaining signal integrity through group-specific training parameters.
3Productivity
If the number of data pins is increased to provide high bandwidth, then data processing speed is improved, but training time and training resources increase as the number of pins increases
Solution Approach 1:
The patent merges multiple data pins into groups and performs collective training on each group, enabling high-bandwidth interfaces with many pins to undergo training more efficiently. This approach allows the system to achieve high data processing speed through increased pin count while reducing training time through grouped processing of multiple pins simultaneously.
Data Source
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AI summary
A memory device comprising: a first pin group including a first data pin configured to transmit or receive a first data signal and a first control pin configured to transmit or receive a first control signal; a second pin group including a second data pin configured to transmit or receive a second data signal and a second control pin configured to transmit or receive a second control signal; a third control pin configured to receive a write data strobe signal; first power pins configured to receive a first power voltage, the first power pins being located in a first power area positioned in each of a first region in which the first pin group is located and a second region in which the second pin group is located; second power pins configured to receive a second power voltage different from the first power voltage, the second power pins being located in a second power area positioned between the first region and the second region; ground pins configured to receive a ground voltage, the ground pins being located in the second power area; and a write data strobe tree circuitry configured to transmit a first internal write data strobe signal with a first toggle timing to a first circuit block corresponding to the first pin group and to transmit a second internal write data strobe signal with a second toggle timing to a second circuit block corresponding to the second pin group, based on the write data strobe signal, wherein the first toggle timing is different from the second toggle timing. The memory device is configured to determine a training value including transmission timing or receiving timing for each pin group based on training at least one pin from each group.