DRAM ODT Resistance Tuning for Per-DQ Signal Reflection Control
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Solution Overview
Problem
Conventional DRAM devices struggle to adjust on-die termination (ODT) resistance values individually for each chipset or DQ, leading to signal reflection issues, particularly in high-capacity memory systems like servers.
Innovation Solution
A DRAM device with a memory controller that measures and sets ODT resistance values for each rank, chipset, and DQ, using a mode register set and training to ensure optimal impedance matching, thereby minimizing signal reflection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single ODT resistance value is adjusted in the DRAM device, then the device can maintain simple control structure, but it cannot adjust ODT resistance values for each chipset or DQ individually
Solution Approach 1:
The patent divides the ODT resistance adjustment capability into separate controllable units for each chipset and DQ. The memory controller can independently adjust ODT resistance values for different chipsets and DQs within the DRAM device, allowing fine-grained control while maintaining the ability to manage multiple termination values simultaneously.
Solution Approach 2:
The patent implements dynamic ODT resistance adjustment where the memory controller can change resistance values based on detected signal quality and system requirements. The system transitions from static single-value adjustment to dynamic multi-value adjustment, enabling optimization for different operating conditions.
2Reliability
If ODT resistance values are not adjusted for each chipset or DQ, then the device structure remains simple, but signal reflection occurs in high-capacity memory systems
Solution Approach 1:
The memory controller detects signal quality metrics (such as eye diagram parameters) and uses this feedback information to automatically adjust ODT resistance values for specific chipsets or DQs. This closed-loop control ensures optimal signal integrity while adapting to varying system conditions without manual intervention.
Solution Approach 2:
The patent changes the resistance parameter values of ODT resistors dynamically based on detected signal quality. The memory controller adjusts resistance values within specific ranges for different chipsets and DQs, transforming the system from fixed impedance to adaptable impedance matching.
3Ease of manufacture
If conventional single ODT adjustment is used, then manufacturing and control are simplified, but signal reflection cannot be prevented in multi-rank systems
Solution Approach 1:
The patent segments the ODT control into per-chipset and per-DQ manageable units, allowing the system to address signal reflection issues in specific locations without affecting the entire DRAM device. This segmented approach simplifies the control implementation compared to a monolithic solution.
Solution Approach 2:
The memory controller performs preliminary detection of signal quality during initialization or training phases, and pre-adjusts ODT resistance values before actual data transmission begins. This preliminary action prevents signal reflection from occurring during operation rather than correcting it after the fact.
Data Source
AI summary
Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.