HBM TSV Bus Switching for Bandwidth Scaling and Timing Sync

The patent divides bank groups into multiple sets (first bank group set, second bank group set, etc.) where each set can be accessed independently through separate TSV buses. This segmentation allows concurrent access to different bank group sets, effectively increasing bandwidth while maintaining timing synchronization within each set. The memory controller can issue commands to different bank group sets without interference, resolving the contradiction between bandwidth and timing synchronization.

The patent introduces dynamic timing parameters (tCCDBG, tCCDLS, tCCDRS) that can be adjusted based on the access pattern and bank group set configuration. These dynamic timing parameters allow the system to optimize timing synchronization for each specific access scenario, enabling bandwidth scaling while maintaining reliable timing margins across different operating conditions.

By segmenting bank groups into multiple sets that can be accessed concurrently, the patent achieves higher effective bandwidth without needing to reduce timing margins on individual access paths. Each bank group set maintains adequate timing margins while the overall system throughput increases through parallel access, thus avoiding the power consumption penalty associated with tight timing margins.

The patent employs periodic timing cycles (tCCDBG, tCCDLS, tCCDRS) that are optimized for each bank group set access pattern. This periodic structure allows the system to maintain consistent, reliable timing margins while achieving high bandwidth through efficient utilization of multiple access cycles, thereby avoiding the need for reduced timing margins that would increase power consumption.

The patent simplifies concurrent access control by segmenting bank groups into distinct sets, where each set can be independently addressed and accessed. The memory controller maintains separate timing parameters for each bank group set, which simplifies the synchronization logic compared to managing timing for all bank groups uniformly. This segmentation reduces timing synchronization complexity while enabling high-capacity concurrent data transmission.

The patent introduces bank group set identifiers and intermediate timing parameters (tCCDBG, tCCDLS, tCCDRS) that act as mediators between the memory controller and individual bank groups. These intermediaries simplify the control logic by providing a structured way to manage concurrent accesses, reducing the complexity of timing synchronization while maintaining high data transmission capacity.

The patent segments the traditional single TSV bus per channel into multiple TSV buses, with each bus serving a specific bank group set. This segmentation enables bandwidth scaling by allowing concurrent data transmission through multiple TSV buses while keeping each individual bus structure simple and manageable. The overall device structure remains relatively simple due to the modular organization of bank group sets and their corresponding TSV buses.

The patent transitions from a single-dimension bus architecture (one TSV bus per channel) to a multi-dimensional architecture where bank groups are organized in sets that can be accessed through multiple TSV buses simultaneously. This dimensional change enables bandwidth scaling without proportionally increasing device complexity, as the additional TSV buses are organized in a structured, manageable manner through the bank group set hierarchy.