3D Memory Array Layout With CMOS Above Array Control
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Solution Overview
Problem
Existing microelectronic device designs face challenges in reducing feature size and improving performance due to the presence of control logic devices that impede size reduction and performance enhancements, such as faster memory cell switching and lower power consumption.
Innovation Solution
Implementing a CMOS above array (CaA) configuration where control circuitry is vertically positioned above the memory array, using oxide-oxide bonding or a combination of oxide-oxide and metal-metal bonding to separate and attach the control circuitry structure from the memory array structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If control logic devices are integrated within the base control logic structure underlying the memory array, then the device can be fabricated with conventional processes, but the horizontal footprint of the memory device increases and performance is impeded
Solution Approach 1:
The patent moves control logic devices from the planar (2D) layout beneath the memory array to a vertical (3D) configuration above the memory array. This dimensional transition reduces the horizontal footprint by utilizing the vertical space above the memory cells, while maintaining electrical connectivity through bonding interfaces between the control circuitry structure and memory array structure.
Solution Approach 2:
The patent divides the microelectronic device into separate structures: the memory array structure and the control circuitry structure. These segmented structures are fabricated independently and then bonded together, allowing each to be optimized separately and reducing the horizontal footprint by distributing components across multiple vertical layers rather than confining them to a single planar layer.
2Device complexity
If control logic devices are integrated within the base control logic structure, then the device structure is simplified, but performance metrics such as memory cell ON/OFF speed and power consumption are degraded
Solution Approach 1:
By positioning control logic devices vertically above the memory array rather than horizontally beneath it, the patent reduces parasitic interconnect lengths and improves signal transmission speed. The vertical stacking reduces the distance between control logic and memory cells, enabling faster ON/OFF switching performance while maintaining a modular structure that can be fabricated using conventional processes.
3Ease of manufacture
If control logic devices are positioned within the base control logic structure, then routing and contact structures can be formed conventionally, but power consumption increases due to interference and larger device size
Solution Approach 1:
The vertical stacking configuration reduces the horizontal distance between control logic devices and memory cells, minimizing parasitic resistance and capacitance in routing structures. This reduces the energy required for signal transmission and switching operations, lowering overall power consumption while maintaining compatibility with conventional routing and contact structure fabrication processes.
Solution Approach 2:
The patent extracts control logic devices from the planar base control logic structure and positions them in a separate vertical layer above the memory array. This separation reduces interference effects and allows for optimized routing paths that minimize energy loss, thereby reducing power consumption while maintaining ease of manufacture through standard bonding processes.
Data Source
AI summary
A microelectronic device comprises a periphery circuitry region, bank regions, a control circuitry structure, and a memory array structure. The periphery circuitry region comprises a central sub-region, and two arm sub-regions extending from the central sub-region from the central sub-region in a first horizontal direction. Each of the two arm sub-regions has a different length than the central sub-region in a second horizontal direction orthogonal to the first horizontal direction. The bank regions are horizontally outward of the periphery circuitry region. The control circuitry structure comprises relatively more speed-critical circuitry within a horizontal area of the periphery circuitry region, and relatively less speed-critical circuitry within horizontal areas of the bank regions. The memory array structure vertically underlies the control circuitry structure and comprises arrays of memory cells within the horizontal areas of the bank regions. Additional microelectronic devices and memory devices are also described.