Memory Array Fly Word Lines for Faster Edge Cell Access
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Solution Overview
Problem
Existing integrated circuit (IC) devices face challenges in reducing word line loading and timing delays due to increased resistance and capacitance, particularly when accessing memory cells at the edges of the memory array, which limits access speed and increases power consumption.
Innovation Solution
Implementing a fly word line configuration using both front side and back side word lines, where one word line 'flies' over a segment of the memory row without electrical coupling, and the other is physically shorter, reducing capacitance and resistance, thereby improving access speed and reducing word line loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional word line configuration is used to access memory cells, then the memory array can be accessed, but the resistance and capacitance increase particularly when accessing memory cells at the edges of the memory array, which limits access speed
Solution Approach 1:
The word line is divided into two separate word lines: a first word line that electrically couples to memory cells in a first segment of the memory row, and a second word line that electrically couples to memory cells in a second segment of the memory row. This segmentation reduces the length of each word line segment, thereby reducing resistance and capacitance and improving access speed for edge memory cells.
Solution Approach 2:
The patent introduces a vertical dimension by forming the first and second word lines at different heights or layers. The first word line is positioned to access memory cells in the first segment while the second word line accesses memory cells in the second segment, utilizing spatial separation in the vertical dimension to reduce electrical interference and signal delays.
2Use of energy by moving object
If a conventional word line configuration is used, then memory cells can be accessed, but the capacitance and resistance increase, which increases power consumption
Solution Approach 1:
By segmenting the word line into two separate lines that each serve specific segments of the memory row, the patent reduces the total capacitance and resistance in the word line structure. This segmentation ensures that each word line segment is shorter and has fewer parasitic elements, thereby reducing power consumption during word line activation.
3Productivity
If both front side and back side word lines are used in a fly word line configuration, then word line loading is reduced and access speed is improved, but the device complexity increases
Solution Approach 1:
The fly word line configuration segments the word line access function into two independent word lines (first word line and second word line) that can operate simultaneously. This segmentation enables parallel access to different memory cell segments, improving productivity while managing complexity through modular design.
Solution Approach 2:
The patent utilizes the vertical dimension by positioning the first and second word lines at different heights or layers, allowing them to coexist without significant electrical interference. This spatial separation in the vertical dimension enables the fly word line configuration to reduce loading while managing overall device complexity.
Data Source
AI summary
An integrated circuit (IC) device includes a memory array including a plurality of memory cells, a first word line over the memory array and electrically coupled to at least one first memory cell among the plurality of memory cells, and a second word line under the memory array and electrically coupled to at least one second memory cell among the plurality of memory cells. The at least one first memory cell and the at least one second memory cell are arranged in a same row of memory cells in the memory array. The first word line and the second word line extend along the row.