Distributed MRAM Array Layout With Shared Read-Write Circuits
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Solution Overview
Problem
Existing memory architectures occupy more layout area than desired, limiting the number of devices that can be included on each integrated circuit chip.
Innovation Solution
Implementing a memory device with shared read and write circuits, where the array circuit is powered off between operations, allowing for more efficient use of layout area and enabling more devices to be included on each integrated circuit chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more MTJ devices are included on each integrated circuit chip to increase speed and performance, then device density and performance are improved, but the layout area occupied by memory architecture increases
Solution Approach 1:
The patent merges the read and write circuits into a single shared circuit that serves multiple MTJ devices. This shared circuit includes a read device and write device that can be selectively activated to perform operations on different MTJ bits, thereby reducing the total number of dedicated circuits needed and decreasing the overall layout area while maintaining high device density
Solution Approach 2:
The shared read/write circuit is designed to perform multiple functions - it can read from and write to different MTJ devices in the array. This multi-functional design allows a single circuit to service multiple memory cells, reducing the per-device circuit overhead and enabling higher device density without proportionally increasing layout area
2Area of stationary object
If a shared read/write circuit is implemented to reduce layout area, then area efficiency is improved, but the time required for operations may increase due to shared access
Solution Approach 1:
The circuit includes dynamic power control where the array circuit is powered off between operations on different MTJ bits. This dynamic powering enables rapid transitions between operational states, allowing the shared circuit to quickly prepare for the next operation by minimizing power consumption during idle periods, thereby reducing overall operation time despite the shared architecture
Solution Approach 2:
The system employs periodic power cycling where the array circuit is powered on during read or write operations and then powered off between operations. This periodic action allows the shared circuit to be quickly reset and prepared for the next operation, reducing the time penalty associated with sharing and enabling fast start-up times
3Loss of energy
If the array circuit is powered off between operations to improve area efficiency and reduce power consumption, then energy efficiency is improved, but the complexity of power management increases
Solution Approach 1:
The power management system is designed to automatically control the power state of the array circuit based on operational requirements. The circuit self-manages its power states by powering on during read/write operations and powering off between operations, eliminating the need for complex external power management infrastructure while achieving significant energy efficiency improvements
Data Source
AI summary
A memory device including an array circuit including a magnetic tunnel junction (MTJ) bit having a logical state and including a set of MTJs is provided. The memory device further includes a read device electrically connected to the MTJ bit and configured to read the logical state of the MTJ bit. The memory device includes a write circuit electrically connected to the MTJ bit and configured to write the logical state of the MTJ bit. The array circuit is powered off between operations on the MTJ bit by the read device and/or the write circuit.