Memory Cell Etch Hard Mask to Prevent Sidewall Shorts

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Solution Overview

Problem

The formation of memory cells in semiconductor devices often results in electrical shorts due to conductive etching by-products from the top electrode mask being redeposited on the sidewalls of the data storage structure during the etching process.

Innovation Solution

A hard mask is used instead of the top electrode mask during the second etch of the data storage structure, preventing the redeposition of conductive by-products and ensuring reliable operation of the memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the top electrode mask is used during etching of the data storage structure, then the etching process can be performed, but conductive etching by-products are redeposited on the sidewalls causing electrical shorts

Engineering Contradiction:
Improveetching precisionVSAvoidelectrical reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent divides the masking function into two separate components: the top electrode mask for defining the top electrode pattern, and a dedicated hard mask layer for protecting the data storage structure sidewalls during etching. This segmentation allows each mask to perform its specific function without causing harmful redeposition, as the hard mask is specifically designed to prevent conductive by-products from reaching the sidewalls.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The hard mask layer acts as an intermediary protective layer between the etching process and the data storage structure sidewalls. It mediates the etching process by providing a non-conductive barrier that prevents conductive etching by-products from redepositing on the sidewalls, while still allowing the etching to proceed through controlled removal of the hard mask in designated areas.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the top electrode mask is used during etching, then the etching can proceed, but conductive by-products are generated that cause electrical shorts

Engineering Contradiction:
Improveetching efficiencyVSAvoidconductive by-products
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent converts the potentially harmful effect of etching by-products into a beneficial process control mechanism. By introducing the hard mask layer, the conductive by-products are redirected to deposit on the hard mask surface rather than on the sensitive data storage structure sidewalls. The hard mask effectively sacrificially accepts the harmful redeposition, protecting the device structure while maintaining etching productivity.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If a hard mask is used instead of the top electrode mask, then redeposition of conductive by-products is prevented, but an additional masking layer is required

Engineering Contradiction:
Improveelectrical reliabilityVSAvoidmasking structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The hard mask layer is designed to serve multiple functions: it acts as a protective barrier during etching, provides a surface for accepting conductive by-products, and can be selectively removed to define the final data storage structure pattern. By making the hard mask multi-functional, the patent reduces the need for separate dedicated components, thereby mitigating the increase in device complexity while maintaining improved reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250359487A1Semiconductor device and method for forming the same
Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250359487A1 patent drawing
  • US20250359487A1 patent drawing
  • US20250359487A1 patent drawing

AI summary

A semiconductor device is provided. The semiconductor device includes a bottom electrode, a top electrode over the bottom electrode, and a data storage structure disposed between the top electrode and the bottom electrode. The semiconductor device further includes a top electrode via (TEVA) electrically coupling the top electrode, and a hard mask pattern disposed over the top electrode and surrounding the TEVA.