Stacked 2-Transistor Memory Cells for Higher Density Storage
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Solution Overview
Problem
Conventional volatile memory devices face challenges in increasing storage density due to physical limitations and fabrication constraints when shrinking memory cell size.
Innovation Solution
A memory device with stacked tiers of two-transistor memory cells and a charge storage structure, utilizing separate conductive regions for access lines and shared conductive structures for data lines, which improves device area efficiency and reduces capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is shrunk to increase storage density, then device storage density is improved, but physical limitations and fabrication constraints are encountered
Solution Approach 1:
The patent transitions from planar memory cell layouts to a three-dimensional stacked architecture with multiple tiers of memory cells vertically positioned over a substrate. This vertical stacking enables increased storage density without further shrinking individual cell dimensions, thereby avoiding the fabrication constraints associated with miniaturization while still achieving higher capacity per unit area.
Solution Approach 2:
The memory device is divided into multiple discrete tiers, each containing separate memory cells with distinct charge storage structures. This segmentation allows each tier to be independently fabricated and positioned, enabling modular scaling of storage density without requiring proportional reduction in individual cell size, thus circumventing physical and fabrication limitations.
2Reliability
If conventional capacitor structures are used in memory cells, then information storage is achieved, but device area efficiency is reduced
Solution Approach 1:
The charge storage structures are positioned in multiple vertical tiers rather than occupying horizontal plane space. This vertical arrangement allows information storage functionality to be maintained while significantly reducing the footprint area required per storage element, thereby improving device area efficiency without sacrificing storage reliability.
Solution Approach 2:
Multiple tiers of memory cells share common data line conductive structures that extend vertically through the device. This merging of conductive pathways across tiers reduces the total number of separate data lines required, improving area efficiency while maintaining reliable information storage access across all tiers.
3Reliability
If separate conductive structures are used for each data line, then signal integrity is maintained, but capacitive coupling between data lines increases
Solution Approach 1:
Dielectric materials are positioned between adjacent data line conductive structures to act as electrical intermediaries that reduce capacitive coupling. This allows separate data lines to maintain their signal integrity while the dielectric mediation minimizes harmful electromagnetic interference and capacitive effects between neighboring conductors.
Solution Approach 2:
The harmful capacitive coupling effect is extracted and isolated by positioning dielectric materials specifically between data lines. This separates the useful function of signal transmission from the harmful effect of capacitive interference, allowing data lines to remain separate for signal integrity while reducing coupling through strategic dielectric placement.
Data Source
AI summary
Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a first conductive structure, a second conductive structure, a conductive portion coupled to one of the conductive structures, and a memory cell. The memory cell includes different semiconductor portions located on different levels of the apparatus and separated from each other by a dielectric portion. The first semiconductor portion is coupled to the first and second conductive structures. The second semiconductor portion is coupled to the first conductive structure. The memory cell includes a charge storage structure coupled to the second semiconductor portion. The charge storage structure includes multiple portions. Part of the conductive portion is located between portions of the charge storage structure and separated from the charge storage structure by a dielectric material.