Multi-Port SRAM Layout With Shared Gates for Smaller Cell Area
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Solution Overview
Problem
Multi-port SRAM cells, particularly in the deep sub-micron era, face challenges with large cell sizes due to inefficient area usage, which hinders further scaling and increases manufacturing complexity.
Innovation Solution
Implementing gate-all-around (GAA) transistors with optimized active region and gate structure layouts, including shared and cut-metal-gate features, to enhance area utilization and reduce non-functional transistors, thereby optimizing cell size and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional multi-port SRAM cell layouts are used, then functional density is maintained, but cell area becomes excessively large
Solution Approach 1:
The patent merges multiple transistor functions into shared gate structures. Specifically, multiple pull-up transistors share a common gate structure, and multiple pass-gate transistors share common gate structures. This consolidation reduces the total number of discrete transistor components while maintaining the multi-port functionality, directly reducing cell area without sacrificing functional density
Solution Approach 2:
The patent implements universal gate structures that serve multiple functions simultaneously. A single gate structure controls multiple transistors that are involved in different read and write operations across multiple ports. This multi-functionality allows the same physical structure to support complex multi-port operations, reducing the area required per functional unit
2Area of stationary object
If cell size is reduced for scaling, then manufacturing complexity increases
Solution Approach 1:
The patent segments the gate structures into distinct modular units that can be independently formed and controlled. Each shared gate structure is a self-contained module that can be manufactured using standard CMOS processes. This segmentation allows the complex multi-port cell to be built from simpler, repeatable units, reducing manufacturing complexity despite the reduced cell size
Solution Approach 2:
The patent transitions from planar transistor layouts to vertically-integrated gate structures where multiple transistors are stacked or arranged in three-dimensional configurations around shared gate regions. This dimensional change allows more functionality to be packed into a smaller footprint without proportionally increasing manufacturing steps, as the vertical integration can be achieved through standard deposition and etching processes
3Area of stationary object
If shared gate structures are implemented, then area utilization improves, but transistor functionality must be carefully managed
Solution Approach 1:
The patent implements dynamic control of shared gate structures through independently controlled gate lines for different ports. Each shared gate can be selectively activated or deactivated based on the current operation (read or write on specific ports). This dynamic control allows the same physical gate structure to serve different functional roles at different times, maximizing area utilization while managing complexity through temporal multiplexing
Solution Approach 2:
The patent introduces intermediate control logic and gate line structures that mediate between the multiple ports and the shared transistor structures. These intermediary elements coordinate the operation of shared gates, ensuring that conflicts between simultaneous read and write operations are resolved. The intermediaries absorb much of the control complexity, allowing the shared gate structures themselves to remain relatively simple
Data Source
AI summary
A memory cell includes first and second active regions extending lengthwise in a first direction, and first, second, third, and fourth gate structures arranged in order from first to fourth along the first direction. Each of the first, second, third, and fourth gate structures extends lengthwise in a second direction that is perpendicular to the first direction. The first, second, third, and fourth gate structures are configured to engage the first and second active regions in forming first, second, third, fourth, fifth, and sixth transistors of a write-port of the memory cell. The memory cell also includes a fifth gate structure configured to engage the second active region in forming a seventh transistor of a read-port of the memory cell.