CFET Nanosheet Gate Layout for Scaled Process Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices as feature sizes continue to decrease, making fabrication processes increasingly complex and difficult.
Innovation Solution
The manufacturing of a complementary field-effect transistor (CFET) device involves forming fin structures, patterning gate all around (GAA) transistor structures, and using advanced processes like double-patterning or multi-patterning to create patterns with smaller pitches, ultimately leading to the formation of channel regions with multiple horizontal nanosheets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then productivity and cost efficiency are improved, but manufacturing precision and process control become more difficult
Solution Approach 1:
The patent applies segmentation by dividing the gate structure into multiple discrete gates (first gate, second gate, third gate, fourth gate) arranged in a specific pattern around the channel. This segmentation allows for independent control and formation of each gate, enabling precise manufacturing at smaller feature sizes while maintaining overall device functionality and density.
Solution Approach 2:
The patent transitions from planar 2D gating to three-dimensional all-around gating by positioning gates above, below, and on the sides of the channel. This dimensional change enables better electrostatic control and threshold voltage tuning without increasing lateral footprint, thus maintaining productivity while improving manufacturability at scaled dimensions.
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved, but device reliability becomes more difficult to maintain
Solution Approach 1:
The patent applies local quality by assigning different threshold voltages to different gates through selective doping or material composition. The first and second gates have one threshold voltage while the third and fourth gates have a different threshold voltage, allowing local optimization of device performance and reliability in different regions of the same device structure.
Solution Approach 2:
The patent utilizes parameter changes by varying the threshold voltage parameter across different gates to optimize device behavior. By adjusting threshold voltages locally, the device can maintain reliable operation at scaled dimensions where uniform gating would be insufficient for controlling leakage and switching characteristics.
3Manufacturing precision
If complex patterning processes are used to create smaller pitches, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies asymmetry in the arrangement and properties of the four gates, with the first and second gates having different characteristics from the third and fourth gates. This asymmetric design allows for simplified patterning processes while achieving the desired pitch control, as not all gates require identical formation steps.
Solution Approach 2:
The patent achieves multi-functionality by using a repeating pattern of gates that can be formed using similar fabrication steps. The first gate and third gate share characteristics, as do the second and fourth gates, allowing universal formation processes to be applied repeatedly, thus reducing overall device complexity while maintaining precise pitch control.
Data Source
AI summary
A semiconductor device includes a fin, first source/drain regions, second source/drain regions, a first nanosheet, a second nanosheet and a metal gate structure. The fin extends in a first direction and protrudes above an insulator. The first source/drain regions are over the fin. The second source/drain regions are over the first source/drain regions. The first nanosheet extends in the first direction between the first source/drain regions. The second nanosheet extends in the first direction between the second source/drain regions. The metal gate structure is over the fin and between the first source/drain regions. The metal gate structure extends in a second direction different from the first direction from a first sidewall to a second sidewall. A first distance in the second direction between the first nanosheet and the first sidewall is smaller than a second distance in the second direction between the first nanosheet and the second sidewall.