CFET Nanosheet Structure with Split Spacer Dielectrics
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Solution Overview
Problem
CFET transistor devices face issues where N-type and P-type transistors have the same semiconductor material, similar electrostatic properties, and shared crystallographic orientation, hindering optimization of electron and hole transport.
Innovation Solution
A CFET transistor device with distinct semiconductor nanosheets, insulating layer, and grids made of different materials and orientations, along with low-permittivity dielectric spacers, to dissociate electrical and electrostatic properties of N-type and P-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same semiconductor material is used for both N-type and P-type transistor channels, then the manufacturing process is simplified, but the optimization of electron transport for N-type and hole transport for P-type transistors is prevented
Solution Approach 1:
The patent divides the semiconductor channel into two distinct nanosheets: a first semiconductor nanosheet for the N-type transistor and a second semiconductor nanosheet for the P-type transistor. This segmentation allows each nanosheet to be made from different semiconductor materials with optimized crystallographic orientations, enabling independent optimization of electron transport in the N-type and hole transport in the P-type transistor while maintaining a unified manufacturing process.
2Ease of manufacture
If the same crystallographic orientation is used for both N-type and P-type transistors, then the manufacturing process is simplified, but the optimization of carrier transport is hindered
Solution Approach 1:
The patent applies different crystallographic orientations to different parts of the device: the first semiconductor nanosheet for the N-type transistor has a first crystallographic orientation optimized for electron transport, while the second semiconductor nanosheet for the P-type transistor has a second crystallographic orientation optimized for hole transport. This local differentiation of material properties enables optimal carrier transport in each transistor type while maintaining compatibility with standard manufacturing processes.
3Ease of manufacture
If identical internal spacers are used for both N-type and P-type transistors, then the manufacturing process is simplified, but independent tuning of electrical and electrostatic properties is prevented
Solution Approach 1:
The patent employs different internal spacer materials for the N-type and P-type transistors: a first internal spacer material for the N-type transistor and a second internal spacer material for the P-type transistor. These different materials provide distinct dielectric properties, allowing independent optimization of electrostatic control and electrical characteristics for each transistor type. This approach enables fine-tuning of device parameters without requiring separate manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances optimization of electron and hole transport by allowing independent tuning of N-type and P-type transistor properties, reducing parasitic capacitances, and improving device performance.
Implementation Method 1
first and second internal spacers comprising first and second dielectric materials with low permittivity respectively, the first and second dielectric materials being different from each other
Data Source
Figure 1
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AI summary
The present description relates to a CFET transistor device (100), comprising: - a substrate (102); - a first semiconductor nanosheet (104) and a second semiconductor nanosheet (106); - an insulating layer (108) disposed between the first and second nanosheets; - a first gate (110) disposed around a first part (112) of the first nanosheet, and a second gate (114) disposed around a first part (116) of the second nanosheet; - first internal spacers (128) disposed against second parts (130) of the first nanosheet between which the first part of the first nanosheet is disposed, and - second internal spacers (132) disposed against second parts (134) of the second nanosheet between which the first part is disposed;and wherein the first and second internal spacers comprise first and second dielectric materials with low permittivity and different from each other.