CFET Nanosheet Gate Stack With Dipole-Tuned Threshold Voltages
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving higher device density and better gate control in nanosheet FETs as transistor dimensions are scaled down, requiring further improvements in three-dimensional designs.
Innovation Solution
The implementation of complementary field effect transistors (CFETs) with multi-threshold voltage schemes, where a first nanosheet FET is vertically stacked on a second nanosheet FET, and the interfacial layer and high-K dielectric layer are selectively doped or intermixed with p-dipole and n-dipole metals to provide different threshold voltages for p-channel and n-channel nanosheet FETs, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency and cost are improved, but gate control and device performance deteriorate due to short-channel effects
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet channel structures where the gate electrode completely surrounds the channel in all directions (top, bottom, and sidewalls). This 3D gate-all-around configuration provides superior electrostatic control over the channel, effectively suppressing short-channel effects that plague scaled-down planar transistors while maintaining high device density.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials combined with metal gate electrodes, and multi-layer nanosheet channels with different semiconductor materials (e.g., Si/SiGe). These composite structures enable better gate control and threshold voltage tuning, allowing the device to maintain reliable operation at scaled dimensions while improving overall device performance and density.
2Ease of manufacture
If conventional planar FET structures are used, then fabrication is simpler, but device density and performance are limited
Solution Approach 1:
The patent adopts vertical stacking of multiple nanosheet channels and complementary FET structures in the third dimension, dramatically increasing device density within the same footprint. This 3D architecture achieves higher productivity without requiring excessively complex fabrication, as it builds upon adapted versions of conventional planar processing techniques combined with selective epitaxial growth and etching.
Solution Approach 2:
The patent divides the channel into multiple discrete nanosheet segments stacked vertically, with each nanosheet forming an independent conducting path. This segmentation allows each nanosheet to be controlled by the surrounding gate electrode, improving overall device density and performance while maintaining fabrication feasibility through modular construction approaches.
3Device complexity
If single threshold voltage is used for both p-channel and n-channel FETs, then device structure is simpler, but functionality and efficiency are reduced
Solution Approach 1:
The patent implements different threshold voltages for p-channel and n-channel FETs by selectively doping or intermixing the interfacial layer and high-k dielectric layer with p-dipole and n-dipole metals in specific regions. This local differentiation of electrical properties allows each transistor type to be optimized for its specific function, improving overall device versatility and efficiency while maintaining a unified complementary FET structure.
Solution Approach 2:
The patent modifies the electrical parameters of the gate dielectric stack by introducing dipole layers with different orientations and magnitudes. By changing the dipole moment parameters in the interfacial and high-k dielectric layers, the threshold voltage of each FET type is tuned independently, enabling optimized performance for both p-channel and n-channel devices within the same integrated structure.
Data Source
AI summary
A semiconductor device structure is provided. The structure includes a plurality of semiconductor layers vertically stacked, a dielectric spacer disposed between two adjacent semiconductor layers of the plurality of semiconductor layers, a first gate electrode layer, a second gate electrode layer disposed immediately adjacent to the first gate electrode layer, a first intermixed layer surrounding the first gate electrode layer, a second intermixed layer surrounding the second electrode layer, a high-K (HK) dielectric layer disposed immediately adjacent to a first side of the dielectric spacer, and a dielectric material disposed immediately adjacent to a second side of the dielectric spacer.