CFET OTP Memory Layout with Overlapping Channels
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Solution Overview
Problem
The scaling down of transistors in semiconductor storage devices has led to increased off-current and power consumption, necessitating the development of three-dimensional transistors, but existing layouts for one-time programmable (OTP) memory cells using complementary FETs (CFETs) have not been adequately explored for efficient integration and area reduction.
Innovation Solution
A layout structure for a small-area OTP memory cell using CFETs, where first and second program transistors with overlapping channel portions are implemented in different layers, and switch transistors are positioned to enable efficient data storage and reading, allowing for correct data retrieval even when gate oxide film breakdown is incomplete, and facilitating faster read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are scaled down to improve integration degree and operating speed, then integration density increases, but off current increases and power consumption increases
Solution Approach 1:
The patent transitions from planar two-dimensional transistor layouts to three-dimensional vertically stacked CFET structures. By stacking program transistors and switch transistors in the vertical dimension, the design achieves higher integration density without further lateral scaling, thereby avoiding the off-current and power consumption issues associated with excessive scaling.
Solution Approach 2:
The patent merges program transistors and switch transistors into a single vertically stacked CFET structure. The program transistor is positioned in the upper layer while the switch transistor is in the lower layer, with shared source/drain regions. This merging reduces the total device area and improves integration density while maintaining proper electrical isolation through the gate oxide structure.
2Area of stationary object
If three-dimensional CFET structures are implemented to reduce area, then integration density improves, but layout complexity increases
Solution Approach 1:
The patent segments the memory cell into distinct vertical layers: the upper layer contains program transistors (TP0, TP1) while the lower layer contains switch transistors (TS0, TS1). This segmentation allows independent optimization of each transistor type's layout while sharing common source/drain regions, reducing overall complexity compared to fully three-dimensional structures.
Solution Approach 2:
The vertically stacked CFET structure serves multiple functions within a single footprint: program transistors for data programming, switch transistors for data reading, and shared source/drain regions for electrical connections. This multi-functionality reduces the number of separate components needed, simplifying the overall layout despite the three-dimensional architecture.
3Productivity
If program transistors and switch transistors are stacked vertically to reduce area, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements a nested structure where the lower-layer switch transistor is positioned directly beneath the upper-layer program transistor, sharing common source/drain regions. This nesting approach with aligned channel portions reduces the lateral footprint while maintaining vertical stacking, thereby reducing alignment precision requirements compared to offset stacked configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This layout structure enables the implementation of two OTP bits in a small area, reduces power consumption, and ensures reliable data reading by utilizing overlapping channel portions of transistors, thereby addressing the challenges of scaling and integration in semiconductor storage devices.
Implementation Method 1
by breaking the thinner portion of the gate oxide film, a state of '1' or '0' is stored in the memory
Data Source
AI summary
A layout structure of a small-area one time programmable (OTP) memory using a complementary FET (CFET) is provided. The OTP memory has transistors TP as a program element and transistors TS as a switch element. The transistors TP are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The transistors TS are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The OTP memory of two bits is implemented in a small area.