Read-Only Memories TRIZ Cases

Memory device multiplies read currents with unique values to generate distinct sums, enabling analog bit storage without increasing circuit complexity.

A nonvolatile memory device architecture with multiple mats uses a control circuit to select and apply specific voltage levels to word-lines and bit-lines.

Global wear leveling rotates data between drives to reduce skew and extend subsystem lifetime despite uneven I/O patterns.

Differentiated drain turn-on voltages narrow threshold voltage distributions and reduce program operation time in non-volatile memory devices.

A memory sub-system touch-up component reprograms cells with charge loss using NAND copyback operations.

Adjusting verify windows prevents over-programming risk while reducing total programming time.

Multiple string select lines apply distinct voltages to reduce program disturbance and enlarge the memory window in NAND flash arrays.

Dynamic voltage regulation eliminates fixed high voltage generation, reducing power consumption and device area by pumping only until threshold is exceeded.

A source potential regulation circuit references bit line voltages to a page source line rather than chip ground.

A semiconductor device uses a command decoder to generate preparation and control signals for a voltage generation circuit.

A nonvolatile memory array performs feedforward and recurrent operations in artificial neural networks by applying input voltages to cells.

A pre-charge transistor control circuit manages data line drivers in memory devices.

A memory controller records program information in a list to track operation status across multiple memory blocks and pages.

A charge pump control circuit switches between active read and leakage modes to manage output voltage.

A memory controller evaluates background leakage to select between default and boosted write voltages.

A sense amplifier uses precharge and charge transfer transistors to manage bit line voltage levels for memory cell data detection.

A memory device executes a de-trap operation to remove trapped electrons from the gate insulation film during program verify.

A complementary FET layout uses overlapping three-dimensional transistor channels to store two one-time programmable bits in a compact footprint.

SGD and SGS switches manage channel voltage during read operations to minimize gate-induced drain leakage in 3D memory arrays.

A semiconductor storage device arranges transistors across distinct chip configurations to enable high density integration in the X direction.

A source gate electrically isolates non-selected pillars from the silicon well to prevent unintended programming during read operations.

Adaptive timing control in NAND EEPROM page buffers resolves threshold voltage discrepancies by adjusting read operations according to programmed cell states.

Adaptive body bias compensates for temperature variations and programming cycles, reducing read errors in NAND flash storage without continuous energy drain.

Precharging nodes to equal voltage accelerates read speed by eliminating repeated capacitor charging for offset compensation.

Parallel page buffers connect to a shared common line for pass/fail verification.

A nonvolatile memory array uses control logic to identify over-erased cells and apply a correction pulse during erase suspend operations.

A write bias voltage generator limits current draw in word line drivers, reducing setup time and improving write speed in non-volatile memory devices.

A semiconductor memory device uses a sensing circuit to output pass or fail signals for page buffer groups during program verification operations.

Partitioning flash memory blocks into multi-bit and single-bit regions resolves the contradiction between storage capacity and data retention reliability.

Sequential read bias variation resolves the trade-off between increased bit density and deteriorated read accuracy in nonvolatile memory cells.

A nonvolatile semiconductor memory device charges bit lines to specific voltages based on program states.

Preliminary cell state detection reduces corrective read latency from three times to two times normal duration.

A sense amplifier circuit uses a current mirror to amplify cell current based on erase count.

Stepwise write control voltage adjustment merges write and verification read cycles to reduce total write operation time while maintaining data reliability.

Adjusts program pulse duration based on temperature to reduce channel boosting, maintaining narrow threshold voltage distributions and improving bit error rate.

A memory controller decouples sense amplifiers using a fixed timing signal.

A signal converter and latch unit process dynamic read signals from complementary global bit lines into stable digital outputs.

A read process compensates for floating gate coupling by intermixing operations with adjacent cells to determine target data states.

A semiconductor controller adjusts read data volume based on health monitoring information.

Segmented drain select lines enable independent string control in 3D memory holes, resolving integration stability trade-offs.

A solid-state drive assigns a dedicated wear indicator block to monitor device health through accelerated program and erase cycles.

Discharging select lines prior to word lines prevents local boosting and read disturbance, ensuring data reliability in the memory cell array.

Dual-level voltage pulses prevent erroneous setting during the resetting operation of nonvolatile semiconductor memory devices.

A boost circuit generates a damage voltage to physically destroy non-volatile memory cells.

Shared bitlines toggle between data output and virtual ground states, resolving the trade-off between storage density and device reliability.

Selective parameter updates reduce data transfer delays and latency by transferring only changed values to non-volatile memory control registers.

A non-volatile memory programming method adjusts bit line voltages based on pass cell counts to narrow threshold voltage distribution.

A memory page buffer applies a controlled read bias arrangement to enhance sensing accuracy in multi-level cell architectures.

Non-volatile memory cells execute matrix multiplication via voltage ramping, reducing device footprint and cost by merging storage with computation.