Source Potential Regulation Circuit for Non-Volatile Memory IR Drop

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Solution Overview

Problem

Conventional non-volatile memory devices face source line bias errors due to finite resistance in the ground loop, leading to inaccurate sensing operations, especially when sensing a large number of memory cells in parallel.

Innovation Solution

The implementation of a memory device with a source potential regulation circuit and a source isolation switch, along with a non-linear resistive element between the aggregate node and ground reference, helps to compensate for source line bias errors by referencing the bit line and word line voltages to a page source line rather than the chip's ground, ensuring accurate sensing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a large number of memory cells are sensed in parallel, then productivity is improved, but source line bias errors increase due to finite resistance in the ground loop

Engineering Contradiction:
Improvesensing speedVSAvoidsensing accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The sensing circuit employs feedback mechanisms to compensate for source line bias errors. The circuit monitors the actual voltage at the source line and adjusts the reference voltage accordingly, ensuring accurate sensing even when multiple memory cells are sensed in parallel. This feedback approach allows the system to maintain high productivity while preserving measurement precision.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The invention changes the reference voltage parameter dynamically based on the actual source line potential. By adjusting the reference voltage to account for the voltage drop across the ground loop resistance, the system can accurately sense memory cell states regardless of the number of cells being sensed in parallel, thus maintaining both speed and accuracy.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If ground loop resistance is reduced, then source line bias errors are minimized, but device complexity increases due to additional regulation circuits

Engineering Contradiction:
Improvesensing accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The invention introduces an intermediary regulation circuit between the ground loop and the sensing circuit. This intermediary element (the source potential regulation circuit) actively compensates for the voltage drop caused by ground loop resistance, effectively mediating the interaction between the ground loop and the sensing circuit. This allows the system to achieve high precision without requiring the ground loop resistance to be extremely low.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The regulation circuit uses feedback to dynamically adjust the source potential, compensating for the effects of ground loop resistance. By continuously monitoring and adjusting the source line voltage, the circuit eliminates the need for extremely low resistance ground loops, thereby reducing the complexity requirements of the ground loop design while maintaining high sensing accuracy.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7764547B2Regulation of source potential to combat cell source IR drop
Publication Date: 2010.07.27 SANDISK TECHNOLOGIES LLC
  • US7764547B2 patent drawing
  • US7764547B2 patent drawing
  • US7764547B2 patent drawing

AI summary

Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.