Dual Bit ROM Cell Using Virtual Ground for Density
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Solution Overview
Problem
Existing single transistor ROM bitcells face challenges in achieving high density, speed, and low voltage operation due to the trade-off between bitcell density and device width, with smaller transistors leading to increased variability and reduced reliability.
Innovation Solution
The implementation of a single transistor ROM bitcell design that stores two bits using a shared virtual ground line and bit lines, allowing for high density and fast operation by using a virtual ground generation circuit to control bit line polarities and via connections, thereby eliminating the need for additional ground lines and increasing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor size is reduced to increase bitcell density, then storage density is improved, but device variability increases and reliability decreases
Solution Approach 1:
The patent merges two bitcells into a single shared structure with common transistors and bit lines. Specifically, bitcell column 0 and bitcell column 1 share source/drain regions and bit lines, effectively combining their functionality into a unified physical structure. This merging allows the system to achieve high density while maintaining reliability because the shared components are designed to handle the combined load, and the structure eliminates the need for smaller, more variable individual transistors.
Solution Approach 2:
The patent implements multi-functionality where single physical components serve multiple bitcells. The shared source/drain regions and bit lines perform functions for both bitcell column 0 and bitcell column 1 simultaneously. This universal design allows the same physical structure to store and access multiple bits of data, achieving high density without requiring proportionally more individual transistor components, thereby avoiding the reliability issues associated with miniaturization.
2Ease of operation
If additional ground lines are added to improve read operation control, then reading capability is improved, but device complexity and area increase
Solution Approach 1:
The patent makes bit lines multi-functional by allowing them to serve as both data output lines and virtual ground lines. During read operations, the bit line that is not currently outputting data is repurposed as a virtual ground line to provide the necessary reference potential. This eliminates the need for dedicated ground lines, reducing device complexity while maintaining full read operation control capability.
Solution Approach 2:
The patent implements dynamic reconfiguration of bit line functions. The role of bit lines switches between data output and virtual ground based on the current read operation requirements. This dynamic assignment allows the same physical lines to adapt to different operational needs, providing full control capability without requiring static, dedicated ground line infrastructure.
3Quantity of substance
If two bits are stored per physical width to increase density, then storage capacity is improved, but read operation complexity increases
Solution Approach 1:
The patent uses periodic time-multiplexed read operations to access different bits. The read operation alternates between outputting data on different bit lines at different time periods. During each period, specific bit lines are activated as output lines while others serve as virtual grounds. This periodic switching allows two bits to be read from the merged bitcell structure without requiring simultaneous complex routing, effectively managing read operation complexity while achieving high storage capacity.
Data Source
AI summary
Disclosed is a ROM memory including a first bitcell including a transistor to store two bits and first and second bit lines to read data stored in the bitcell, a second bitcell including a second transistor connected to the first transistor and sharing the first and second bit lines, and a virtual ground line adjacent the bit lines configured to ground the bitcells.