Flash Memory Block Segmentation for Capacity-Reliability Trade-off
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Solution Overview
Problem
Multi-bit flash memory devices are less reliable than single-bit devices due to sensitivity to charge trapping and tunnel oxide layer stress, leading to increased system costs as they are used for simple data storage while critical data is stored in single-bit memories.
Innovation Solution
A nonvolatile memory device with a memory cell array partitioned into multi-bit and single-bit storage regions, utilizing a judgment circuit to determine the type of storage region for each block address, a read/write circuit for selective operations, and an error checking and correction circuit with both multi-bit and single-bit ECC units operating based on a flag signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit flash memory devices are used for data storage, then storage capacity is improved, but reliability deteriorates due to sensitivity to charge trapping and tunnel oxide layer stress
Solution Approach 1:
The memory device is divided into multiple memory blocks, where each block can be independently configured as either single-bit or multi-bit storage. This segmentation allows critical data to be stored in reliable single-bit blocks while non-critical data utilizes higher-capacity multi-bit blocks, resolving the contradiction between storage capacity and reliability through spatial division of functions.
Solution Approach 2:
The memory device implements dynamic configurability where each memory block can be programmed and switched between single-bit and multi-bit operating modes based on data requirements. This dynamic adaptation allows the system to optimize between capacity and reliability on-demand, enabling multi-bit operation for non-critical data and single-bit operation for critical data within the same device.
2Reliability
If single-bit flash memory devices are used for critical data storage, then reliability is improved, but system cost increases due to requiring separate memory devices
Solution Approach 1:
The patent merges both single-bit and multi-bit memory capabilities into a single integrated memory device. Multiple memory blocks are consolidated within one device package, with each block configurable for its optimal operating mode. This merging eliminates the need for separate single-bit and multi-bit memory devices, reducing system complexity and cost while maintaining high reliability for critical data.
Solution Approach 2:
The memory device achieves multi-functionality by enabling each memory block to operate in either single-bit or multi-bit mode based on configuration. This universal design allows the same physical device to serve both high-reliability single-bit storage and high-capacity multi-bit storage functions, replacing the need for multiple specialized devices and simplifying the overall system architecture.
3Productivity
If memory blocks are configured for multi-bit storage, then storage efficiency is improved, but error correction requirements increase due to lower reliability
Solution Approach 1:
Different error correction strategies are applied locally to different memory blocks based on their configuration. Multi-bit blocks use stronger error correction codes suitable for their lower reliability characteristics, while single-bit blocks use simpler error correction appropriate for their higher reliability. This localized adaptation of error correction mechanisms allows each block to achieve optimal storage efficiency while maintaining adequate error resistance for its specific operating mode.
Data Source
AI summary
There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal. An error checking and correction (ECC) circuit including a multi-bit ECC unit and a single-bit ECC unit for checking and correcting an error in a data of the read/write circuit can also be included.