Variable Resistive Memory Resetting via Dual-Level Pulse Control
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Solution Overview
Problem
In nonvolatile semiconductor memory devices using unipolar-type variable resistive elements, the close proximity of set and reset voltages can lead to erroneous setting during the resetting operation due to parasitic resistances, causing issues with maintaining the high resistance state.
Innovation Solution
A control circuit is implemented to manage the pulse voltage applied to the variable resistive element, increasing it to a first voltage and then decreasing it to a second voltage lower than the first but higher than ground voltage during the resetting operation, thereby preventing erroneous setting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high voltage is applied to the variable resistive element during resetting operation to generate sufficient Joule heat for phase change, then the resetting speed is improved, but the risk of erroneous setting increases because the reset voltage becomes close to the set voltage
Solution Approach 1:
The patent applies periodic voltage pulses with specific timing characteristics. A reset voltage pulse is applied for a predetermined time period, and if the element hasn't reset by the end of this period, a set voltage pulse is applied to ensure proper state. This periodic control prevents erroneous setting while achieving complete resetting.
Solution Approach 2:
The patent dynamically changes voltage parameters based on timing. The reset voltage is applied only for a specific duration, and the voltage level is adjusted according to the elapsed time. This parameter control ensures sufficient Joule heat generation for resetting while preventing the voltage from remaining at levels that could cause erroneous setting.
2Device complexity
If the set voltage and reset voltage are kept close to each other to reduce voltage difference requirements, then the device complexity is reduced, but the parasitic resistance in wires causes erroneous setting during resetting
Solution Approach 1:
The patent applies a reset voltage pulse in advance for a predetermined time period before attempting to set the element. This preliminary resetting action ensures that any potential erroneous setting caused by parasitic resistance is prevented, as the element is deliberately reset before the set operation begins.
Solution Approach 2:
The patent implements a feedback mechanism where the system monitors whether the resetting operation was successful within the predetermined time period. Based on this feedback, the control circuit decides whether to apply additional set voltage pulses, thereby adapting to the actual state of the variable resistive element and preventing erroneous settings.
3Reliability
If a longer pulse width is used during resetting operation to ensure complete state change, then the resetting reliability is improved, but the energy consumption increases due to prolonged high voltage application
Solution Approach 1:
The patent uses periodic voltage pulses with optimized duration. Instead of applying continuous high voltage, the system applies reset voltage pulses for specific time intervals, allowing the element to change state efficiently while minimizing energy consumption. The periodic nature ensures complete resetting without prolonged energy input.
Solution Approach 2:
The patent rushes through the resetting process by applying high voltage for a brief, optimized duration sufficient to achieve phase change. Rather than maintaining voltage indefinitely, the system quickly completes the resetting action and transitions to the next operation, thereby reducing total energy consumption while ensuring reliable state change.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a more precise control of the resetting operation, reducing the likelihood of erroneous setting and enabling efficient switching between resistance states in a nonvolatile semiconductor memory device.
Implementation Method 1
a model of causing a phase change by heat generation is dominant. Therefore, it is expected that when the voltage of a reset pulse is set to be high, a generation amount of Joule heat increases (J=V·I·t)
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a variable resistive element are connected in series; and a control circuit configured to selectively drive the first wires and the second wires. The control circuit executes a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state. At a time of executing the resetting operation, the control circuit increases a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreases the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage.